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M25P10-VMN6T
1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface
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PRELIMINARY DATAJune 2000
M25P101 Mbit Low Voltage Paged Flash Memory
With 20 MHz Serial SPI Bus Interface 1 Mbit PAGED Flash Memory 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL 256 Kbit SECTOR ERASE IN 1 s TYPICAL BULK ERASE IN 2 s TYPICAL SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 20 MHz CLOCK RATE AVAILABLE SUPPORTS POSITIVE CLOCK SPI MODES DEEP POWER DOWN MODE (1 μA TYPICAL) ELECTRONIC SIGNATURE 10,000 ERASE/PROG CYCLES PER SECTOR 20 YEARS DATA RETENTION –40 TO 85°C TEMPERATURE RANGE
DESCRIPTIONThe M25P10 is an 1 Mbit Paged Flash Memory
fabricated with STMicroelectronics High
Endurance CMOS technology. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
The device connected to the bus is selected when
the chip select input (S) goes low. Data is clocked
in during the low to high transition of clock C, data
Table 1. Signal Names
M25P10
is clocked out during the high to low transition of
clock C
SIGNALS DESCRIPTION
Serial Output (Q)
The output pin is used to transfer data serially out
of the memory. Data is shifted out on the falling
edge of the serial clock.
Serial Input (D)
The input pin is used to transfer data serially into
the device. It receives instructions, addresses,
and the data to be programmed. Input is latched
on the rising edge of the serial clock.
Serial Clock (C)
The serial clock provides the timing of the serial
interface. Instructions, addresses, or data present
at the input pin are latched on the rising edge of
the clock input, while data on the Q pin changes
after the falling edge of the clock input.
Chip Select (S)
When S is high, the memory is deselected and the
Q output pin is at high impedance and, unless an
internal Read, Program, Erase or Write Status
Register operation is underway, the device will be
in the Standby Power mode (this is not the Deep
Power Down mode). S low enables the memory,
placing it in the active power mode. It should be
noted that after power-on, a high to low transition
on S is required prior to the start of any operation.
Hold (HOLD)
The HOLD pin is used to pause serial
communications with a SPI memory without
resetting the serial sequence. To take the Hold
condition into account, the product must be
selected. The HOLD condition is validated by a 0
state on the Hold pin synchronized with the 0 state
on the Clock, as shown in Figure 4. The DeHOLD
condition is validated by a 1 state on the Hold pin
synchronized with the 0 state on the Clock. During
the Hold condition D, Q, and C are at a high
impedance state.
When the memory is under HOLD condition, it is
possible to deselect the device. Then, the protocol
is reset. The memory remains on HOLD as long as
the Hold pin is Low. To restart communication with
the device, it is necessary to both DeHOLD (H =
1) and to SELECT the memory.
Write Protect (W)
This pin is for hardware write protection of the
Status Register (SR); except WIP and WEL bits.
When bit 7 (SRWD) of the status register is 0 (the
initial delivery state); it is possible to write the SR
once the WEL (Write Enable Latch) has been set
with the WREN instruction and whatever is the
status of pin W (high or low).
Table 2. Absolute Maximum Ratings 1
Note:1. Except for the rating “Ambient Operating Temperature Range”, stresses above those listed in this table may cause permanent
damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those
indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
3/21
M25P10
Once bit 7 (SRWD) of the status register has been
set to 1, the possibility to rewrite the SR depends
on the logical level present at pin W:
–If W pin is high, it will be possible to rewrite the
status register after having set the WEL (Write
Enable Latch).
–If W pin is low, any attempt to modify the status
register will be ignored by the device even if the
WEL was set. As a consequence: all the data
bytes in the memory area software protected
(SPM) by the BPi bits of the status register are
also hardware protected against data
modification and can be seen as a Read Only
memory area. This mode is called the Hardware
Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) by setting SRWD bit after pulling
down the W pin or by pulling down the W pin after
setting SRWD bit.
The only way to abort the Hardware Protected
Mode once entered is to pull high the W pin.
If W pin is permanently tied to high level, the
Hardware Protected Mode will never be activated
and the memory will only allow the user to
software protect a part of the memory with the BPi
bits of the status register.
All protection features of the device are
summarized in Table 3.
M25P10
Clock Polarity (CPOL) and Clock Phase
(CPHA) with SPI Bus
As shown in Figure 5, the M25P10 can be driven
by a microcontroller with its SPI peripheral running
in either of the two following modes: (CPOL,
CPHA) = (’0’, ’0’) or (CPOL, CPHA) = (’1’, ’1’). For
these two modes, input data is latched in by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).The difference between (CPOL, CPHA) = (0,
0) and (CPOL, CPHA) = (1, 1) is the clock polarity
when in stand-by: C remains at ’0’ for (CPOL,
CPHA) = (0, 0) and C remains at ’1’ for (CPOL,
CPHA) = (1, 1) when there is no data transfer.
MEMORY ORGANIZATION
The memory is organized in 131,072 words of 8
bits each. The device features 1,024 pages of 128
bytes each. Each page can be individually
programmed (bits are programmed from ‘1’ to ’0’
state).
The device is also organized in 4 sectors of
262,144 bits (32,768 x 8 bits) each.The device is
Sector or Bulk Erasable but not Page Erasable
(bits are erased from ’0’ to ’1’ state).
OPERATIONS
All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any
Table 3. Protection Features
Note:1. SPM: Software Protected Mode. HPM: Hardware Protected Mode. BPi: Bits BP0 and BP1 of the Status Register. WEL: Write Enable Latch of the Status Register. W: Write Protect Input Pin. SRWD: Status Register Write Disable Bits of the Status Register. The device is Bulk Erasable if, and only if, (BP0, BP1) = (0, 0), (see Bulk Erase paragraph).
Table 4. Memory Organization
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M25P10
Table 5. Protected Area Sizes
M25P10
operation, a one-byte instruction code must be
sent to the chip. This code is entered via the data
input (D), and latched on the rising edge of the
clock input (C). To enter an instruction code, the
device must have been previously selected (S =
low). Table 6 shows the available instruction set.
At Power-up and Power-down, the device must
not be selected (that is the S input must follow the
voltage applied on the VCC pin) until the supply
voltage reaches the correct VCC values which are
VCC(min) at Power-up and VSS at Power-down (a
simple pull-up resistor on S insures safe and
proper power up and down phases).
Read Data Byte(s) (READ)
The device is first selected by putting S low. The
Read instruction byte is followed by a three bytes
address (A23-A0), each bit being latched-in during
the rising edge of the clock (C). Then the data
stored in the memory at the selected byte address
is shifted out on the Q output pin, each bit being
shifted out during the falling edge of the clock (C).
The first byte addressed can be any byte within a
page. The address is automatically incremented to
the next higher address after each byte of data is
shifted out. The whole memory can therefore be
read with a single Read instruction. When the
highest address is reached, the address counter
rolls over to 000000h allowing the read cycle to be
continued indefinitely.
The Read operation is terminated by deselecting
the chip. The chip can be deselected at any time
during data output. Any read attempt during an
Erase, Program or Write Status Register cycle will
be rejected and will deselect the chip without
having any effects on the ongoing operation.
The timing sequence is shown in Figure 11.
Page Program (PP)
Prior to any Page Program attempt, a write enable
instruction (WREN) must have been previously
sent (the S input driven low, WREN instruction
properly transmitted and the S input driven high).
After the WREN instruction decoding, the memory
sets the Write Enable Latch (WEL) which allows
the execution of any further Page Program
instruction. The Page Program instruction is
entered by driving the Chip select input (S) low,
followed by the instruction byte, 3 address bytes
and at least 1 data byte on Data In input (D). If the
least significant address bits differ from [A6-
A0]=000.0000, all transmitted data exceeding the
addressed page boundary will roll over and will be
programmed from address [A6-A0]=000.0000 of
this same page. The Chip Select input (S) must be
driven low for the entire duration of the sequence.
Table 6. Instruction Set
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M25P10
If more than 128 bytes are sent to the device,
previously latched data are discarded and the last
128 data bytes are guaranteed to be programmed
correctly within the same page. If less than 128
Data bytes are sent to device; they are correctly
programmed at the requested addresses without
having any effects on the other bytes of the same
Page.
The device must be deselected just after the
eighth bit of the last data byte has been latched in.
If not, the Page Program instruction is not
executed. As soon as the device is deselected, the
self-timed Page Program cycle (tPP) is initiated.
While the Page Program cycle is in progress, the
status register may be read to check the WIP bit
value. WIP is high during the self-timed Page
Program cycle and is low when it is completed.
When the cycle is completed, the write enable
latch (WEL) is reset.
A Page Program instruction applied to a Page
which is software protected by the BPi bits (see
Table 4 and Table 5) is not initiated.
The timing sequence is shown in Figure 12.
Write Enable (WREN) and Write Disable (WRDI)
The Write Enable Latch must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk
Erase (BE) and Write Status Register (WRSR)
operation. The WREN instruction, whose timing
sequence is shown in Figure 7, will set the latch
and the WRDI instruction, whose timing sequence
is shown in Figure 8, will reset the latch.
The Write Enable Latch is reset under the
following conditions: Power on WRDI instruction completion WRSR instruction completion Page Program instruction completion Sector Erase instruction completion Bulk Erase instruction completion.
After completion of either WREN or WRDI
instruction, the chip enters a wait state and waits
for a deselect.
M25P10
Read Status Register (RDSR)
The RDSR instruction provides access to the
Status Register content. The Status Register may
be read at any time, even during a Page Program,
Sector Erase, Bulk Erase or Write Status Register.
When one of these instructions is in progress, it is
recommended to check the WIP bit before sending new instruction to the device. For this, it is
possible to continuously read the Status Register
value.
WIP bit: The Write-In-Process (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase operation. When set
to a ’1’, such an operation is in progress, when set
to a ’0’ no such operation is in progress.
WEL bit: The Write Enable Latch (WEL) bit
indicates the status of the internal Write Enable
Latch. When set to a ’1’ the latch is set, when set
to a ’0’ the latch is reset and no Write Status
Register, Program or Erase sequence will be
allowed.
BP1,BP0 bits: The Block Protect bits BPi are non-
volatile bits. They define the size of the area to be
software protected against Program and Erase
operations. These bits are written with the WRSR
instruction (see Table 5). Once (BP0, BP1) are set
to a value different from (0,0), the relevant area
becomes protected against Page Program and
Sector Erase operations. BPi bits can be written
provided that the Hardware Protected Mode has
not been set. The Bulk Erase instruction is
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M25P10
the execution of any further WRSR instruction.
The WRSR instruction is entered by driving the
Chip select input (S) low, followed by the
instruction byte and the data byte on Data In input
(D). WRSR instruction has no effect on b6, b5, b4,
b1 and b0 of the Status Register. b6, b5 and b4 are
always read at ’0’.
The device must be deselected just after the
eighth bit of the data byte has been latched in. If
not, the WRSR instruction is not executed. As
soon as the device is deselected, the self-timed
Write Status Register cycle (tW) is initiated. While
the Write Status Register cycle is in progress, the
Status Register may still be read to check the WIP
bit value. WIP is high during the self-timed Write
Status Register cycle and is low when it is
completed. When the cycle is completed, the write
enable latch (WEL) is reset.
The WRSR instruction allows the user to define
the size of the software Protected area (Read
Only) when setting the BP1,BP0 values, according
to Table 4. The WRSR instruction also allows the
user to set or reset the SRWD bit in accordance
with the W pin. SRWD bit and W pin allow the part
to be put in the Hardware protected mode (please
see the sections entitled “Read Status Register
(RDSR)” on page 8, “Write Protect (W)” on page 2,
and Table 3). WRSR instruction has no effect on
internally taken into account if, and only if, (BP0,
BP1) = (0,0).
SRWD bit: The SRWD bit operates together with
the W pin. SRWD bit and W pin allow the part to
be put in the Hardware protected mode. In this
mode (W pin = 0 and SRWD = 1), the non-volatile
bits of the Status Register (SRWD, BP1, BP0)
become read only bits and the Write Status
Register (WRSR) instruction has no more effect
on the device (please see the section entitled
“Write Protect (W)” on page 2, and Table 3).
Write in the Status Register (WRSR)
Prior to any WRSR instruction, a write enable
instruction (WREN) must have been previously
sent (the S input driven low, WREN instruction
properly transmitted and the S input driven high).
After the WREN instruction decoding, the memory
sets the Write Enable Latch (WEL) which allows
Table 7. Status Register Format
Note:1. SRWD, BP0 and BP1 are non-volatile read and write bits. WEL and WIP are volatile read-only bits (WEL is set and
reset by specific instructions; WIP is automatically set
and reset by the internal logic of the device).
b7 b0
M25P10
the device once the Hardware Protected Mode is
entered.
The timing sequence is shown in Figure 10.
Sector Erase (SE)
Prior to any Sector Erase attempt, a write enable
instruction (WREN) must have been previously
sent (the S input driven low, WREN instruction
properly transmitted and the S input driven high).
After the WREN instruction decoding, the memory
sets the Write Enable Latch (WEL) which allows
the execution of any further Sector Erase. The
Sector Erase instruction is entered by driving the
Chip select input (S) low, followed by the
instruction byte and 3 address bytes on Data In
input (D). Any address of the Sector (see Table 4)
is a valid address for the Sector Erase instruction.
The Chip Select input (S) must be driven low for
the entire duration of the sequence. The device
must be deselected just after the eighth bit of the
last address byte has been latched in. If not, the
Sector Erase instruction is not executed. As soon
as the device is deselected, the self-timed Sector
Erase cycle (tSE) is initiated. While the Sector
Erase cycle is in progress, the status register may
be read to check the WIP bit value. WIP is high
during the self-timed Sector Erase cycle and is low
when it is completed. When the cycle is
completed, the write enable latch (WEL) is reset.
A Sector Erase instruction applied to a Sector
which is software protected by the BPi bits (see
Table 4 and Table 5) is not initiated.
The timing sequence is shown in Figure 13.
Bulk Erase (BE)
Prior to any Bulk Erase attempt, a write enable
instruction (WREN) must have been previously
sent (the S input driven low, WREN instruction
properly transmitted and the S input driven high).
After the WREN instruction decoding, the memory
M25P10
sets the Write Enable Latch (WEL) which allows
the execution of any further Bulk Erase. The Bulk
Erase instruction is entered by driving the Chip
select input (S) low, followed by the instruction
byte on Data In input (D).
The Chip Select input (S) must be driven low for
the entire duration of the sequence. The device
must be deselected just after the eighth bit of the
instruction byte has been latched in. If not, the
Bulk Erase instruction is not executed. As soon as
the device is deselected, the self-timed Bulk Erase
cycle (tBE) is initiated. While the Bulk Erase cycle
is in progress, the status register may be read to
check the WIP bit value. WIP is high during the
self-timed Bulk Erase cycle and is low when it is
completed. When the cycle is completed, the write
enable latch (WEL) is reset.
The Bulk Erase instruction is internally taken into
account if, and only if, (BP0, BP1) = (0,0). In other
words, the Bulk Erase instruction is ignored if at
least one Sector is software protected. In this case
the Bulk Erase instruction is discarded and none of
the Sectors are erased.
The timing sequence is shown in Figure 14.
Enter Deep Power Down Mode (DP)
After Power-on, when S is high, the memory is
deselected, the Q output pin is at high impedance
and the device is in the Standby Power Mode state
(ICC1). Under this state, the Memory waits for a
select condition and is able to receive, decode and
execute all instructions.This mode is not the Deep
Power Down Mode which is entered by the way of specific instruction. The purpose of the Deep
Power down mode is to drastically reduce the
standby current from ICC1 to ICC2 (see Table 10).
Once the device has entered the Deep Power
Down Mode, all instructions are ignored except the
RES instruction which releases the part from this
