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LPC3141FET180NXPN/a65avaiARM926EJ-S with 192 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller
LPC3143FET180NXPN/a2266avaiARM926EJ-S with 192 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller, Decryption Engine


LPC3143FET180 ,ARM926EJ-S with 192 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller, Decryption EngineBlock diagram JTAGinterfaceLPC3141/3143TEST/DEBUGINTERFACEUSB 2.0DMAARM926EJ-SHIGH-SPEEDCONTROLLERO ..
LPC3152FET208 ,ARM926EJ-S with 192 kB SRAM, USB High-speed (OTG, Host, Device), SD/MMC, NAND flash controller LPC3152/3154ARM926EJ microcontrollers with USB High-speed OTG, SD/MMC, NAND flash controller, and ..
LPC3154FET208 ,ARM926EJ-S with 192 kB SRAM, USB High-speed (OTG, Host, Device), SD/MMC, NAND flash controller, AESGeneral descriptionThe NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0 ..
LPC3180FEL320 ,16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interfacefeaturesn ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, runningat up to 2 ..
LPC3180FEL320 ,16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interfaceBlock diagramVFP9 ETB ETM9USB transceiver interfaceD-TCM I-TCM0 kB 0 kBARM9EJSD-CACHE I-CACHE32 kB ..
LPC3220FET296 ,ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controllerFeatures and benefits ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz. Vector Flo ..
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LPC3141FET180-LPC3143FET180
ARM926EJ-S with 192 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller
1. General description
The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four
channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted
at consumer, industrial, medical, and communication markets. To optimize system power
consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock
Generation Unit (CGU) that provides dynamic clock gating and scaling.
2. Features and benefits
2.1 Key features
CPU platform 270 MHz, 32-bit ARM926EJ-S 16 kB D-cache and 16 kB I-cache Memory Management Unit (MMU) Internal memory 192 kB embedded SRAM External memory interface NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only) 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM Security AES decryption engine (LPC3143 only) Secure one-time programmable memory for AES key storage and customer use 128 bit unique ID per device for DRM schemes Communication and connectivity High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY Two I2 S interfaces Integrated master/slave SPI Two master/slave I2 C-bus interfaces Fast UART Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA Four-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface System functions Dynamic clock gating and scaling Multiple power domains
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers with USB
High-speed OTG, SD/MMC, and NAND flash controller
Rev. 1 — 4 June 2012 Product data sheet
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB On the LPC3143 only: secure booting using an AES decryption engine from SPI
flash, NAND flash, SD/MMC cards, UART, or USB. DMA controller Four 32-bit timers Watchdog timer PWM module Master/slave PCM interface Random Number Generator (RNG) General Purpose I/O pins (GPIO) Flexible and versatile interrupt structure JTAG interface with boundary scan and ARM debug access Operating voltage and temperature Core voltage: 1.2 V I/O voltages: 1.8 V, 3.3 V Temperature: 40 C to +85C TFBGA180 package: 12 x 12 mm, 0.8 mm pitch
3. Ordering information

3.1 Ordering options

Table 1. Ordering information

LPC3141FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12  12  0.8 mm SOT570-3
LPC3143FET180 TFBGA180 Plastic thin fine pitch ball grid array package, 180 balls, body 12  12  0.8 mm SOT570-3
Table 2. Ordering options for LPC3141/3143

LPC3141FET180 270/90 MHz 192 kB no Device/Host/OTG 4 2 each yes 40 C to +85C
LPC3143FET180 270/ MHz
192 kB yes Device/
Host/OTG 2 each yes 40 C to +85C
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
4. Block diagram

NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
5. Pinning information
5.1 Pinning

Table 3. Pin allocation table
Row A
Row B
Row C
Row D
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
Row E
Row F
Row G
Row H
Row J
Row K
Row L
Row M
Row N
Table 3. Pin allocation table …continued
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

Row P
Table 3. Pin allocation table …continued
Table 4. Pin description

Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
Clock Generation Unit (CGU)

FFAST_IN A10 SUP1 AI - AIO2 12 MHz oscillator clock input.
FFAST_OUT B10 SUP1 AO - AIO2 12 MHz oscillator clock output.
VDDA12 D11;
E10
SUP1 Supply - PS3 12 MHz oscillator/PLLs analog supply.
VSSA12 E9 - Ground - CG1 12 MHz oscillator/PLLs analog ground.
RSTIN_N H14 SUP3 DI I:PU DIO2 System Reset Input (active LOW).
CLK_256FS_O H12 SUP3 DO O DIO1 Programmable clock output; fractionally
derived from CLK1024FS_BASE clock
domain. Generally used for external audio
codec master clock.
CLOCK_OUT J4 SUP4 DO O DIO4 Programmable clock output; fractionally
derived from SYS_BASE clock domain.
SYSCLK_O[4] G13 SUP3 DO O DIO1 Programmable clock output. Output one of
seven base/reference input clocks. No
fractional divider.
10-bit ADC

ADC10B_VDDA33 A13 SUP3 Supply - PS3 10-bit ADC analog supply.
ADC10B_GNDA A12 - Ground - CG1 10-bit ADC analog ground.
ADC10B_GPA0 B14 SUP3 AI - AIO1 10-bit ADC analog input.
ADC10B_GPA1 A14 SUP3 AI - AIO1 10-bit ADC analog input.
ADC10B_GPA2 B13 SUP3 AI - AIO1 10-bit ADC analog input.
ADC10B_GPA3 C14 SUP3 AI - AIO1 10-bit ADC analog input.
USB HS 2.0 OTG

USB_VBUS L2 SUP5 AI - AIO3 USB supply detection line.
USB_ID M1 SUP3 AI - AIO1 Indicates to the USB transceiver whether in
device (USB_ID HIGH) or host (USB_ID
LOW) mode (contains internal pull-up
resistor).
USB_RREF J5 SUP3 AIO - AIO1 USB connection for external reference
resistor (12 k  1) to analog ground
supply.
USB_DP P2 SUP3 AIO - AIO1 USB D+ connection with integrated 45 
termination resistor.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

USB_DM N2 SUP3 AIO - AIO1 USB D connection with integrated 45 
termination resistor.
USB_VDDA12_PLL L1 SUP1 Supply - PS3 USB PLL supply.
USB_VDDA33_DRV M2 SUP3 Supply - PS3 USB analog supply for driver.
USB_VDDA33 P1 SUP3 Supply - PS3 USB analog supply for PHY.
USB_VSSA_TERM L3 - Ground - CG1 USB analog ground for clean reference for
on chip termination resistors.
USB_GNDA N1 - Ground - CG1 USB analog ground.
USB_VSSA_REF K4 - Ground - CG1 USB analog ground for clean reference.
JTAG

JTAGSEL N11 SUP3 DI I:PD DIO1 JTAG selection. Controls output function of
SCAN_TDO and ARM_TDO signals. Must
be LOW during power-on reset.
TDI K9 SUP3 DI I:PU DIO1 JTAG data input.
TRST_N P13 SUP3 DI I:PD DIO1 JTAG TAP Controller Reset Input. Must be
LOW during power-on reset.
TCK M14 SUP3 DI I:PD DIO1 JTAG clock input.
TMS P10 SUP3 DI I:PU DIO1 JTAG mode select input.
SCAN_TDO F10 SUP3 DO O/Z DIO1 JTAG TDO signal from scan TAP controller.
Pin state is controlled by JTAGSEL.
ARM_TDO E11 SUP3 DO O DIO1 JTAG TPO signal from ARM926 TAP
controller.
BUF_TRST_N F11 SUP3 DO O DIO1 Buffered TRST_N out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
BUF_TCK D13 SUP3 DO O DIO1 Buffered TCK out signal. Used for connecting
an on board TAP controller (FPGA, DSP,
etc.).
BUF_TMS D14 SUP3 DO O DIO1 Buffered TMS out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
UART

mUART_CTS_N [4][5] N13 SUP3 DI/GPIO I DIO1 UART clear to send (active LOW).
mUART_RTS_N [4][5] P14 SUP3 DO/GPIO O DIO1 UART ready to send (active LOW).
UART_RXD[4] P12 SUP3 DI/GPIO I DIO1 UART serial input.
UART_TXD[4] N12 SUP3 DO/GPIO O DIO1 UART serial output.2 C-bus master/slave interface
I2C_SDA0 C10 SUP3 DIO I IICD I2 C0-bus serial data line.
I2C_SCL0 D10 SUP3 DIO I IICC I2 C0-bus serial clock line.
I2C_SDA1[4] E12 SUP3 DIO O DIO1 I2 C1-bus serial data line.
I2C_SCL1[4] E13 SUP3 DIO O DIO1 I2 C1-bus serial clock line.
Table 4. Pin description …continued

Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
Serial Peripheral Interface (SPI)

SPI_CS_OUT0[4] A7 SUP3 DO O DIO4 SPI chip select output (master).
SPI_SCK[4] A8 SUP3 DIO I DIO4 SPI clock input (slave)/clock output (master).
SPI_MISO[4] C8 SUP3 DIO I DIO4 SPI data input (master)/data output (slave).
SPI_MOSI[4] B7 SUP3 DIO I DIO4 SPI data output (master)/data input (slave).
SPI_CS_IN[4] B8 SUP3 DI I DIO4 SPI chip select input (slave).
Digital power supply

VDDI H3;
L7;
L12;
C12;
SUP1 Supply - CS2 Digital core supply.
VSSI A11;
C7;
D12;
G4;
L6;
L11
Ground - CG2 Digital core ground.
Peripheral power supply

VDDE_IOA B2;
E5;
F5;
G5;
SUP4 Supply - PS1 Peripheral supply for NAND flash interface.
VDDE_IOB L4;
M5;
M7;
SUP8 Supply - PS1 Peripheral supply for SDRAM/LCD.
VDDE_IOC C13;
D5;
D7;
E8;
G12;
L10;
K11
SUP3 Supply - PS1 Peripheral supply.
VSSE_IOA C3;
C4;
E4;
F4;
H4; Ground - PG1 -
VSSE_IOB M3;
M4;
M6; Ground - PG1 -
Table 4. Pin description …continued

Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

VSSE_IOC B12;
D6;
D8;
D9;
G11;
L9;
L13 Ground - PG1 -
LCD interface

mLCD_CSB[4] K8 SUP8 DO O DIO4 LCD chip select (active LOW).
mLCD_E_RD[4] L8 SUP8 DO O DIO4 LCD 6800 enable or 8080 read enable
(active HIGH).
mLCD_RS[4] P8 SUP8 DO O DIO4 LCD instruction register (LOW)/data register
(HIGH) select.
mLCD_RW_WR[4] N9 SUP8 DO O DIO4 LCD 6800 read/write select or 8080 write
enable (active HIGH).
mLCD_DB_0[4] N8 SUP8 DIO O DIO4 LCD data 0.
mLCD_DB_1[4] P9 SUP8 DIO O DIO4 LCD data 1.
mLCD_DB_2[4] N6 SUP8 DIO O DIO4 LCD data 2.
mLCD_DB_3[4] P6 SUP8 DIO O DIO4 LCD data 3.
mLCD_DB_4[4] N7 SUP8 DIO O DIO4 LCD data 4.
mLCD_DB_5[4] P7 SUP8 DIO O DIO4 LCD data 5.
mLCD_DB_6[4] K6 SUP8 DIO O DIO4 LCD data 6.
mLCD_DB_7[4] P5 SUP8 DIO O DIO4 LCD data 7.
mLCD_DB_8[4] N5 SUP8 DIO O DIO4 LCD data 8/8-bit data 0.
mLCD_DB_9[4] L5 SUP8 DIO O DIO4 LCD data 9/8-bit data 1.
mLCD_DB_10[4] K7 SUP8 DIO O DIO4 LCD data 10/8-bit data 2.
mLCD_DB_11[4] N4 SUP8 DIO O DIO4 LCD data 11/8-bit data 3.
mLCD_DB_12[4] K5 SUP8 DIO O DIO4 LCD data 12/8-bit data 4/4-bit data 0.
mLCD_DB_13[4] P4 SUP8 DIO O DIO4 LCD data 13/8-bit data 5/4-bit data 1/serial
clock output.
mLCD_DB_14[4] P3 SUP8 DIO O DIO4 LCD data 14/8-bit data 6/4-bit data 2/serial
data input.
mLCD_DB_15[4] N3 SUP8 DIO O DIO4 LCD data 15/8-bit data 7/4-bit data 3/serial
data output.2 S/digital audio input
I2SRX_DATA0[4] M10 SUP3 DI/GPIO I DIO1 I2 S serial data receive input.
I2SRX_DATA1[4] G14 SUP3 DI/GPIO I DIO1 I2 S serial data receive input.
I2SRX_BCK0[4] N10 SUP3 DIO/GPIO I DIO1 I2 S bit clock.
I2SRX_BCK1[4] F14 SUP3 DIO/GPIO I DIO1 I2 S bit clock.
I2SRX_WS0[4] P11 SUP3 DIO/GPIO I DIO1 I2 S word select.
I2SRX_WS1[4] F13 SUP3 DIO/GPIO I DIO1 I2 S word select.
Table 4. Pin description …continued

Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers2 S/digital audio output

mI2STX_DATA0[4] M13 SUP3 DO/GPIO O DIO1 I2 S serial data transmit output.
mI2STX_BCK0[4] M12 SUP3 DO/GPIO O DIO1 I2 S bit clock.
mI2STX_WS0[4] M11 SUP3 DO/GPIO O DIO1 I2 S word select.
mI2STX_CLK0[4] N14 SUP3 DO/GPIO O DIO1 I2 S serial clock.
I2STX_DATA1[4] F12 SUP3 DO/GPIO O DIO1 I2 S serial data transmit output.
I2STX_BCK1[4] E14 SUP3 DO/GPIO O DIO1 I2 S bit clock.
I2STX_WS1[4] G10 SUP3 DO/GPIO O DIO1 I2 S word select.
General Purpose IO (GPIO)

GPIO0[7] K10 SUP3 GPIO I:PD DIO1 General Purpose IO pin 0 (mode pin 0).
GPIO1[7] J10 SUP3 GPIO I:PD DIO1 General Purpose IO pin 1 (mode pin 1).
GPIO2[7] L14 SUP3 GPIO I DIO1 General Purpose IO pin 2 (mode pin 2).
GPIO3 B11 SUP3 GPIO I DIO1 General Purpose IO pin 3.
GPIO4 C11 SUP3 GPI I DIO1 General Purpose input pin 4.
mGPIO5[4] B6 SUP3 GPIO I DIO4 General Purpose IO pin 5.
mGPIO6[4] A6 SUP3 GPIO I DIO4 General Purpose IO pin 6.
mGPIO7[4] A5 SUP3 GPIO I DIO4 General Purpose IO pin 7.
mGPIO8[4] B5 SUP3 GPIO I DIO4 General Purpose IO pin 8.
mGPIO9[4] C5 SUP3 GPIO I DIO4 General Purpose IO pin 9.
mGPIO10[4] A4 SUP3 GPIO I DIO4 General Purpose IO pin 10.
GPIO11 H13 SUP3 GPIO I DIO1 General Purpose IO pin 11.
GPIO12 H10 SUP3 GPIO I DIO1 General Purpose IO pin 12.
GPIO13 J12 SUP3 GPIO I DIO1 General Purpose IO pin 13.
GPIO14 J14 SUP3 GPIO I DIO1 General Purpose IO pin 14.
GPIO15 J13 SUP3 GPIO I DIO1 General Purpose IO pin 15.
GPIO16 J11 SUP3 GPIO I DIO1 General Purpose IO pin 16.
GPIO17 K12 SUP3 GPIO I DIO1 General Purpose IO pin 17.
GPIO18 K14 SUP3 GPIO I DIO1 General Purpose IO pin 18.
GPIO19 H11 SUP3 GPIO I DIO1 General Purpose IO pin 19.
GPIO20 K13 SUP3 GPIO I DIO1 General Purpose IO pin 20.
External Bus Interface (EBI)/NAND flash controller

EBI_A_0_ALE[4] B3 SUP4 DO O DIO4 EBI address latch enable.
EBI_A_1_CLE[4] A2 SUP4 DO O DIO4 EBI command latch enable.
EBI_D_0[4] G2 SUP4 DIO I DIO4 EBI data I/O 0.
EBI_D_1[4] F2 SUP4 DIO I DIO4 EBI data I/O 1.
EBI_D_2[4] F1 SUP4 DIO I DIO4 EBI data I/O 2.
EBI_D_3[4] E1 SUP4 DIO I DIO4 EBI data I/O 3.
EBI_D_4[4] E2 SUP4 DIO I DIO4 EBI data I/O 4.
Table 4. Pin description …continued

Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

[1] Digital IO levels are explained in Table5.
[2] I = input; I:PU = input with internal weak pull-up; I:PD = input with internal weak pull-down; O = output.
[3] Cell types are explained in Table6.
[4] Pin can be configured as GPIO pin in the IOCONFIG block.
[5] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can be selected to be used for alternative functions: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2).
[6] The polyfuses get unintentionally burned at random if VPP is powered to 2.3 V or greater before the VDDI is powered up to minimum
nominal voltage. This will destroy the sample because randomly blowing security fuses will lock the sample and also can corrupt the
AES key. For this reason it is recommended that VPP be powered by SUP1 at power on.
[7] To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see
UM10362 JTAG chapter for details.
EBI_D_5[4] D1 SUP4 DIO I DIO4 EBI data I/O 5.
EBI_D_6[4] D2 SUP4 DIO I DIO4 EBI data I/O 6.
EBI_D_7[4] C1 SUP4 DIO I DIO4 EBI data I/O 7.
EBI_D_8[4] B1 SUP4 DIO I DIO4 EBI data I/O 8.
EBI_D_9[4] A3 SUP4 DIO I DIO4 EBI data I/O 9.
EBI_D_10[4] A1 SUP4 DIO I DIO4 EBI data I/O 10.
EBI_D_11[4] C2 SUP4 DIO I DIO4 EBI data I/O 11.
EBI_D_12[4] G3 SUP4 DIO I DIO4 EBI data I/O 12.
EBI_D_13[4] D3 SUP4 DIO I DIO4 EBI data I/O 13.
EBI_D_14[4] E3 SUP4 DIO I DIO4 EBI data I/O 14.
EBI_D_15[4] F3 SUP4 DIO I DIO4 EBI data I/O 15.
EBI_DQM_0_NOE[4] H1 SUP4 DO O DIO4 NAND read enable (active LOW).
EBI_NWE[4] J2 SUP4 DO O DIO4 NAND write enable (active LOW).
NAND_NCS_0[4] J1 SUP4 DO O DIO4 NAND chip enable 0.
NAND_NCS_1[4] J3 SUP4 DO O DIO4 NAND chip enable 1.
NAND_NCS_2[4] K1 SUP4 DO O DIO4 NAND chip enable 2.
NAND_NCS_3[4] K2 SUP4 DO O DIO4 NAND chip enable 3.
mNAND_RYBN0[4] E6 SUP4 DI I DIO4 NAND ready/busy 0.
mNAND_RYBN1[4] E7 SUP4 DI I DIO4 NAND ready/busy 1.
mNAND_RYBN2[4] B4 SUP4 DI I DIO4 NAND ready/busy 2.
mNAND_RYBN3[4] D4 SUP4 DI I DIO4 NAND ready/busy 3.
EBI_NCAS_BLOUT_0[4] G1 SUP4 DO O DIO4 EBI lower lane byte select (7:0).
EBI_NRAS_BLOUT_1[4] H2 SUP4 DO O DIO4 EBI upper lane byte select (15:8).
Secure one-time programmable memory

VPP[6] A9;
SUP1/
SUP3
Supply - PS3 Supply for polyfuse programming.
Pulse Width Modulation (PWM)

PWM_DATA[4] B9 SUP3 DO/GPIO O DIO1 PWM output.
Table 4. Pin description …continued

Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

[1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD interface must be the same, i.e. SUP4 and
SUP8 should be connected to the same rail. (See also Section 6.28.3.)
Table 5. Supply domains

SUP1 1.0 V to 1.3 V VDDI, VDDA12, USB_VDDA12_PLL,
VPP (OTP read)
Digital core supply
SUP3 2.7 V to 3.6 V VDDE_IOC, ADC10B_VDDA33,
USB_VDDA33_DRV, USB_VDDA33,
VPP (during OTP write)
Peripheral supply
SUP4 1.65 V to 1.95 V (in 1.8 V
mode)
2.5 V to 3.6 V (in 3.3 V mode)
VDDE_IOA Peripheral supply for NAND flash
interface
SUP5 4.5 V to 5.5 V USB_VBUS USB VBUS voltage
SUP8 1.65 V to 1.95 V (in 1.8 V
mode)
2.5 V to 3.6 V (in 3.3 V mode)
VDDE_IOB Peripheral supply for
SDRAM/SRAM/bus-based LCD [1]
Table 6: I/O pads

DIO1 bspts3chp Digital input/output Bidirectional 3.3 V; 3-state output; 3 ns slew rate control; plain input;
CMOS with hysteresis; programmable pull-up, pull-down, repeater
DIO2 bpts5pcph Digital input/output Bidirectional 5 V; plain input; 3-state output; CMOS with programmable
hysteresis; programmable pull-up, pull-down, repeater
DIO4 mem1
bsptz40pchp
Digital input/output Bidirectional 1.8 V or 3.3 V; plain input; 3-state output; programmable
hysteresis; programmable pull-up, pull-down, repeater
IICC iic3m4scl Digital input/outputI2 C-bus; clock signal
IICD iic3mvsda Digital input/outputI2 C-bus; data signal
AIO1 apio3v3 Analog input/output Analog input/output; protection to external 3.3 V supply rail
AIO2 apio Analog input/output Analog input/output
AIO3 apiot5v Analog input/output Analog input/output; 5 V tolerant pad-based ESD protection
CS1 vddco Core supply -
CS2 vddi Core supply -
PS1 vdde3v3 Peripheral supply -
PS2 vdde Peripheral supply -
PS3 vddco3v3 Analog power
supply
CG1 vssco Core ground -
CG2 vssis Core ground -
PG1 vsse Peripheral ground -
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
6. Functional description
6.1 ARM926EJ-S

The processor embedded in the chip is the ARM926EJ-S. It is a member of the ARM9
family of general-purpose microprocessors. The ARM926EJ-S is intended for
multi-tasking applications where full memory management, high performance, and low
power are important.
This module has the following features: ARM926EJ-S processor core which uses a five-stage pipeline consisting of fetch,
decode, execute, memory and write stages. The processor supports both the 32-bit
ARM and 16-bit Thumb instruction sets, which allows a trade off between high
performance and high code density. The ARM926EJ-S also executes an extended
ARMv5TE instruction set which includes support for Java byte code execution. Contains an AMBA BIU for both data accesses and instruction fetches. Memory Management Unit (MMU). 16 kB instruction and 16 kB data separate cache memories with an 8 word line length.
The caches are organized using Harvard architecture. Little endian is supported. The ARM926EJ-S processor supports the ARM debug architecture and includes logic
to assist in both hardware and software debugging. Supports dynamic clock gating for power reduction. The processor core clock can be set equal to the AHB bus clock or to an integer
number times the AHB bus clock. The processor can be switched dynamically
between these settings. ARM stall support.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
6.2 Memory map

6.3 JTAG

The Joint Test Action Group (JTAG) interface allows the incorporation of the
LPC3141/3143 in a JTAG scan chain.
This module has the following features:
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
ARM926 debug access Boundary scan The ARM926 debug access can be permanently disabled through JTAG security bits
in the One-Time Programmable memory (OTP) block.
6.4 NAND flash controller

The NAND flash controller is used as a dedicated interface to NAND flash devices.
Figure 4 shows a block diagram of the NAND flash controller module. The heart of the
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An Error
Correction Code (ECC) module allows for hardware error correction for support of
Multi-Level Cell (MLC) NAND flash devices. The NAND flash controller is connected to
the AES block to support secure (encrypted) code execution (see Section 6.21).
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects errors, and/or the AES decryption module can
decrypt data.
This module has the following features: Dedicated NAND flash interface with hardware controlled read and write accesses. Wear leveling support with 516-byte mode. Software controlled command and address transfers to support wide range of flash
devices. Software control mode where the ARM is directly master of the flash device.
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Support for 8-bit and 16-bit flash devices. Support for any page size from 0.5 kB upwards. Programmable NAND flash timing parameters. Support for up to 4 NAND devices. Hardware AES decryption (LPC3143 only). Error Correction Module (ECC) for MLC NAND flash support: Reed-Solomon error correction encoding and decoding. Uses Reed-Solomon code words with 9-bit symbols over GF(29 ), a total codeword
length of 469 symbols, including 10 parity symbols, giving a minimum Hamming
distance of 11. Up to 8 symbol errors can be corrected per codeword. Error correction can be turned on and off to match the demands of the application. Parity generator for error correction encoding. Wear leveling information can be integrated into protected data. Interrupts generated after completion of error correction task with three interrupt
registers. Error correction statistics distributed to ARM using interrupt scheme. Interface is compatible with the ARM External Bus Interface (EBI).
6.5 Multi-Port Memory Controller (MPMC)

The multi-port memory controller supports the interface to different memory types, for
example: SDRAM Low-power SDRAM Static memory interface
This module has the following features: Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM. Address line supporting up to 128 MB (two 64Mx8 devices connected to a single chip
select) of dynamic memory. The MPMC has two AHB interfaces: an interface for accessing external memory. a separate control interface to program the MPMC. This enables the MPMC
registers to be situated in memory with other system peripheral registers. Low transaction latency. Read and write buffers to reduce latency and to improve performance, particularly for
un-cached processors. Static memory features include: asynchronous page mode read programmable wait states bus turnaround delay
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Low-cost, low-power ARM926EJ microcontrollers
output enable and write enable delays extended wait One chip select for synchronous memory and two chip selects for static memory
devices. Power-saving modes. Dynamic memory self-refresh mode supported. Controller support for 2 k, 4 k, and 8 k row address synchronous memory parts. Support for all AHB burst types. Little and big endian support. Support for the External Bus Interface (EBI) that enables the memory controller pads
to be shared.
6.6 External Bus Interface (EBI)

The EBI module acts as multiplexer with arbitration between the NAND flash and the
SDRAM/SRAM memory modules connected externally through the MPMC.
The main purpose for using the EBI module is to save external pins. However only data
and address pins are multiplexed. Control signals towards and from the external memory
devices are not multiplexed.
6.7 Internal Static ROM (ISROM)

The internal static ROM is used to store the boot code of the LPC3141/3143. After a reset,
the ARM processor will start its code execution from this memory.
The LPC3143 ROM memory has the following features: Supports secure booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART,
and USB (DFU class) interfaces. Supports SHA1 hash checking on the boot image. Supports non-secure boot from UART and USB (DFU class) interfaces during
development. Once AES key is programmed in OTP , only secure boot is allowed
through UART and USB. Supports secure booting from managed NAND devices such as moviNAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode. Contains pre-defined MMU table (16 kB) for simple systems.
Table 7. Memory map of the external SRAM/SDRAM memory modules

External SRAM0 0x2000 0000 0x2000 FFFF 8 bit 64 kB
0x2000 0000 0x2001 FFFF 16 bit 128 kB
External SRAM1 0x2002 0000 0x2002 FFFF 8 bit 64 kB
0x2002 0000 0x2003 FFFF 16 bit 128 kB
External SDRAM0 0x3000 0000 0x37FF FFFF 16 bit 128 MB
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Low-cost, low-power ARM926EJ microcontrollers

The LPC3141 ROM memory has the following features: Supports booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and
USB (DFU class) interfaces. Supports option to perform CRC32 checking on the boot image. Contains pre-defined MMU table (16 kB) for simple systems. Supports booting from managed NAND devices such as movi-NAND, iNAND,
eMMC-NAND and eSD-NAND using SD/MMC boot mode.
The boot ROM determines the boot mode based on reset state of GPIO0, GPIO1, and
GPIO2 pins. To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins
TRST_N and JTAGSEL must be LOW during power-on reset (see UM10362 JTAG
chapter for details). Table 8 shows the various boot modes supported on the
LPC3141/3143:
[1] For security reasons this mode is disabled when JTAG security feature is used.
6.8 Internal RAM memory

The ISRAM (Internal Static RAM Memory) controller module is used as controller between
the AHB bus and the internal RAM memory. The internal RAM memory can be used as
working memory for the ARM processor and as temporary storage to execute the code
that is loaded by boot ROM from external devices such as SPI flash, NAND flash, and
SD/MMC cards.
This module has the following features: Capacity of 192 kB
Table 8. LPC3141/3143 boot modes

NAND 0 0 0 Boots from NAND flash. If proper image is not found,
boot ROM will switch to DFU boot mode.
SPI 0 0 1 Boot from SPI NOR flash connected to SPI_CS_OUT0. If
proper image is not found, boot ROM will switch to DFU
boot mode.
DFU 0 1 0 Device boots via USB using DFU class specification.
SD/MMC 0 1 1 Boot ROM searches all the partitions on the
SD/MMC/SDHC/MMC+/eMMC/eSD card for boot image.
If partition table is missing, it will start searching from
sector 0. A valid image is said to be found if a valid image
header is found, followed by a valid image. If a proper
image is not found, boot ROM will switch to DFU boot
mode.
Reserved 0 1 0 0 Reserved for testing.
NOR flash 1 0 1 Boot from parallel NOR flash connected to
EBI_NSTCS_1.[1]
UART 1 1 0 Boot ROM tries to download boot image from UART
((115200 - 8 - n -1) assuming 12 MHz FFAST clock).
Test 1 1 1 Boot ROM is testing ISRAM using memory pattern test.
Switches to UART boot mode on receiving three ASCI
dots ("...") on UART.
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Low-cost, low-power ARM926EJ microcontrollers
Implemented as two independent 96 kB memory banks
6.9 Memory Card Interface (MCI)

The MCI controller interface can be used to access memory cards according to the
Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be
used to interface to small form factor expansion cards compliant to the SDIO card
standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives.
This module has the following features: One 8-bit wide interface. Supports high-speed SD, versions 1.01, 1.10 and 2.0. Supports SDIO version 1.10. Supports MMCplus, MMCmobile and MMCmicro cards based on MMC 4.1. Supports SDHC memory cards. CRC generation and checking. Supports 1/4-bit SD cards. Card detection and write protection. FIFO buffers of 16 byte deep. Host pull-up control. SDIO suspend and resume. 1 to 65 535 byte blocks. Suspend and resume operations. SDIO read-wait. Individual clock and power ON/OFF features to each card. Maximum clock speed of 52 MHz (MMC 4.1). Supports CE-ATA 1.1. Supports 1-bit, 4-bit, and 8-bit MMC cards and CE-ATA devices.
6.10 High-speed Universal Serial Bus 2.0 On-The-Go (OTG)

The USB OTG module allows the LPC3141/3143 to connect directly to a USB host such
as a PC (in device mode) or to a USB device in host mode. In addition, the LPC3141/3143
has a special, built-in mode in which it enumerates as a Device Firmware Upgrade (DFU)
class, and which allows for a (factory) download of the device firmware through USB.
This module has the following features: Complies with Universal Serial Bus specification 2.0. Complies with USB On-The-Go supplement. Complies with Enhanced Host Controller Interface Specification. Supports auto USB 2.0 mode discovery. Supports all high-speed USB-compliant peripherals. Supports all full-speed USB-compliant peripherals.
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Low-cost, low-power ARM926EJ microcontrollers
Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals. Contains UTMI+ compliant transceiver (PHY). Supports interrupts. This module has its own, integrated DMA engine.
6.11 DMA controller

The DMA controller can perform DMA transfers on the AHB without using the CPU.
This module has the following features: Supported transfer types:
Memory to memory copy Memory can be copied from the source address to the destination address with a
specified length, while incrementing the address for both the source and
destination.
Memory to peripheral Data is transferred from incrementing memory to a fixed address of a peripheral.
The flow is controlled by the peripheral.
Peripheral to memory Data is transferred from a fixed address of a peripheral to incrementing memory.
The flow is controlled by the peripheral. Supports single data transfers for all transfer types. Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words. The DMA controller has 12 channels. Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action. Supports byte, half-word, and word transfers and correctly aligns them over the AHB
bus. Compatible with ARM flow control for single requests, last single requests, terminal
count info, and DMA clearing. Supports swapping endian property of the transported data. Table 9: Peripherals that support DMA
NAND flash controller/AES decryption engine[1] Memory to memory
SPI Memory to peripheral and peripheral to memory
MCI Memory to peripheral and peripheral to memory
LCD interface Memory to peripheral
UART Memory to peripheral and peripheral to memory 2C0/1-bus interfaces Memory to peripheral and peripheral to memory
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Low-cost, low-power ARM926EJ microcontrollers

[1] AES decryption engine is available on LPC3143 only.
6.12 Interrupt controller

The interrupt controller collects interrupt requests from multiple devices, masks interrupt
requests, and forwards the combined requests to the processor. The interrupt controller
also provides facilities to identify the interrupt requesting devices to be served.
This module has the following features: The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals. Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM
core. The ARM core supports two distinct levels of priority on all interrupt sources,
FIQ for high priority interrupts and IRQ for normal priority interrupts. Software interrupt request capability associated with each request input. Visibility of interrupts request state before masking. Support for nesting of interrupt service routines. Interrupts routed to IRQ and to FIQ are vectored. Level interrupt support.
The following blocks can generate interrupts: NAND flash controller USB 2.0 HS OTG Event router 10 bit ADC UART LCD interface MCI SPI I2 C0-bus and I2 C1-bus controllers Timer 0, timer 1, timer 2, and timer 3I2 S transmit: I2STX_0 and I2STX_1I2 S receive: I2SRX_0 and I2SRX_1 DMA
6.13 Multi-layer AHB

The multi-layer AHB is an interconnection scheme based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.2 S0/1 receive Peripheral to Memory2 S0/1 transmit Memory to peripheral
PCM interface Memory to peripheral and peripheral to memory
Table 9: Peripherals that support DMA …continued
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Low-cost, low-power ARM926EJ microcontrollers

Multiple masters can have access to different slaves at the same time.
Figure 5 gives an overview of the multi-layer AHB configuration in the LPC3141/3143.
AHB masters and slaves are numbered according to their AHB port number.
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

This module has the following features: Supports all combinations of 32-bit masters and slaves (fully connected interconnect
matrix). Round-Robin priority mechanism for bus arbitration: all masters have the same
priority and get bus access in their natural order. Four devices on a master port (listed in their natural order for bus arbitration): DMA ARM926 instruction port ARM926 data port USB OTG Devices on a slave port (some ports are shared between multiple devices): AHB to APB bridge 0 AHB to APB bridge 1 AHB to APB bridge 2 AHB to APB bridge 3 AHB to APB bridge 4 Interrupt controller NAND flash controller MCI SD/SDIO USB 2.0 HS OTG 96 kB ISRAM 96 kB ISRAM 128 kB ROM MPMC (Multi-Purpose Memory Controller)
6.14 APB bridge

The APB bridge is a bus bridge between AMBA Advanced High-performance Bus (AHB)
and the ARM Peripheral Bus (APB) interface.
The module supports two different architectures: Single-clock architecture, synchronous bridge. The same clock is used at the AHB
side and at the APB side of the bridge. The AHB-to-APB4 bridge uses this
architecture. Dual-clock architecture, asynchronous bridge. Different clocks are used at the AHB
side and at the APB side of the bridge. The AHB-to-APB0, AHB-to-APB1,
AHB-to-APB2, and AHB-to-APB3 bridges use this architecture.
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Low-cost, low-power ARM926EJ microcontrollers
6.15 Clock Generation Unit (CGU)

The clock generation unit generates all clock signals in the system and controls the reset
signals for all modules. The structure of the CGU is shown in Figure 6. Each output clock
generated by the CGU belongs to one of the domains. Each clock domain is fed by a
single base clock that originates from one of the available clock sources. Within a clock
domain, fractional dividers are available to divide the base clock to a lower frequency.
Within most clock domains, the output clocks are again grouped into one or more
subdomains. All output clocks within one subdomain are either all generated by the same
fractional divider or they are connected directly to the base clock. Therefore all output
clocks within one subdomain have the same frequency and all output clocks within one
clock domain are synchronous because they originate from the same base clock.
The CGU reference clock is generated by the external crystal. Furthermore the CGU has
several Phase Locked Loop (PLL) circuits to generate clock signals that can be used for
system clocks and/or audio clocks. All clock sources, except the output of the PLLs, can
be used as reference input for the PLLs.
This module has the following features: Advanced features to optimize the system for low power: All output clocks can be disabled individually for flexible power optimization. Some modules have automatic clock gating: they are only active when (bus)
access to the module is required. Variable clock scaling for automatic power optimization of the AHB bus (high clock
frequency when the bus is active, low clock frequency when the bus is idle). Clock wake-up feature: module clocks can be programmed to be activated
automatically on the basis of an event detected by the event router (see also
Section 6.19). For example, all clocks (including the core/bus clocks) are off and
activated automatically when a button is pressed. Supports five clock sources: Reference clock generated by the oscillator with an external crystal. Pins I2SRX_BCK0, I2SRX_WS0, I2SRX_BCK1 and I2SRX_WS1 are used to input
external clock signals (used for generating audio frequencies in I2SRX slave
mode, see also Section 6.4). Supports two PLLs: System PLL generates programmable system clock frequency from its reference
input.I2 S/Audio PLL generates programmable audio clock frequency (typically 256  fs)
from its reference input.
Remark: Both the System PLL and the I
2 S/Audio PLL generate their frequencies
based on their (individual) reference clocks. The reference clocks can be
programmed to the oscillator clock or one of the external clock signals. Highly flexible switchbox to distribute the signals from the clock sources to the module
clocks. Each clock generated by the CGU is derived from one of the base clocks and
optionally divided by a fractional divider.
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Low-cost, low-power ARM926EJ microcontrollers
Each base clock can be programmed to have any one of the clock sources as an
input clock. Fractional dividers can be used to divide a base clock by a fractional number to a
lower clock frequency. Fractional dividers support clock stretching to obtain a (near) 50% duty cycle
output clock. Register interface to reset all modules under software control. Based on the input of the Watchdog timer (see also Section 6.16), the CGU can
generate a system-wide reset in the case of a system stall.
6.16 Watchdog Timer (WDT)

The watchdog timer can be used to generate a system reset if there is a CPU/software
crash. In addition the watchdog timer can be used as an ordinary timer. Figure 7 shows
how the watchdog timer module is connected in the system.
This module has the following features: In the event of a software or hardware failure, generates a chip-wide reset request
when its programmed time-out period has expired (output m1). Watchdog counter can be reset by a periodical software trigger.
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Low-cost, low-power ARM926EJ microcontrollers
After a reset, a register will indicate whether a reset has occurred because of a
watchdog generated reset. Watchdog timer can also be used as a normal timer in addition to the watchdog
functionality (output m0).
6.17 Input/Output Configuration module (IOCONFIG)

The General Purpose Input/Output (GPIO) pins can be controlled through the register
interface provided by the IOCONFIG module. Next to several dedicated GPIO pins, most
digital IO pins can also be used as GPIO if they are not required for their normal,
dedicated function.
This module has the following features: Provides control for the digital pins that can double as GPIO (next to their normal
function). The pinning list in Table 4 indicates which pins can double as GPIO. Each controlled pin can be configured for 4 operational modes: Normal operation (i.e. controlled by a function block) Driven LOW Driven HIGH High impedance/input A GPIO pin can be observed (read) in any mode. The register interface provides ‘set’ and ‘clear’ access methods for choosing the
operational mode.
6.18 10-bit Analog-to-Digital Converter (ADC10B)

This module is a 10-bit successive approximation ADC with an input multiplexer to allow
for multiple analog signals on its input. A common use of this module is to read out
multiple keys on one input from a resistor network.
This module has the following features: Four analog input channels, selected by an analog multiplexer. Programmable ADC resolution from 2 bit to 10 bit. The maximum conversion rate is 400 kSamples/s for 10 bit resolution and
1500 kSamples/s for 2 bit resolution. Single and continuous analog-to-digital conversion scan modes. Power-down mode.
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Low-cost, low-power ARM926EJ microcontrollers
6.19 Event router

The event router extends the interrupt capability of the system by offering a flexible and
versatile way of generating interrupts. Combined with the wake-up functionality of the
CGU, it also offers a way to wake-up the system from suspend mode (with all clocks
deactivated).
The event router has four interrupt outputs connected to the interrupt controller and one
wake-up output connected to the CGU as shown in Figure 8. The output signals are
activated when an event (for instance a rising edge) is detected on one of the input
signals. The input signals of the event router are connected to relevant internal (control)
signals in the system or to external signals through pins of the LPC3141/3143.
This module has the following features: Provides programmable routing of input events to multiple outputs for use as
interrupts or wake up signals. Input events can come from internal signals or from the pins that can be used as
GPIO. Inputs can be used either directly or latched (edge detected) as an event source. The active level (polarity) of the input signal for triggering events is programmable. Direct events will disappear when the input becomes inactive. Latched events will remain active until they are explicitly cleared. Each input can be masked globally for all inputs at once. Each input can be masked for each output individually. Event detect status can be read for each output separately. Event detection is fully asynchronous (no active clock required). Module can be used to generate a system wake-up from suspend mode.
Remark: All pins that can be used as GPIO are connected to the event router (see

Figure 8). Note that they can be used to trigger events when in normal functional mode or
in GPIO mode.
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Low-cost, low-power ARM926EJ microcontrollers
6.20 Random number generator

The Random Number Generator (RNG) generates true random numbers for use in
advanced security and Digital Rights Management (DRM) related schemes. These
schemes rely upon truly random, i.e. completely unpredictable numbers.
This module has the following features: True random number generator. The random number register does not rely on any kind of reset. The generators are free running in order to ensure randomness and security.
6.21 AES decryption (LPC3143 only)

This module can be used for data decryption using the AES algorithm. The AES module
has the following features: AES-128: 128 bit key, 128 bit data. CBC mode over blocks of 512 bytes. Each block of 512 bytes uses the same initial value. AES can be turned on and off.
6.22 Secure One-Time Programmable memory (OTP)

The Secure One-Time Programmable Memory can be used for storing non-volatile
information like serial number, security bits, etc. It consists of a polyfuse array, embedded
data registers, and control registers. One of the main features of the OTP is storing a
security key and a unique ID.
This module has the following features: 512-bit one-time programmable memory. 128 bits are used for an unique ID which is pre-programmed in the wafer fab. 40 bits are used for security and other features which are programmed at the
customer production line. 184 bits are available for customer use. 32 bits are used for USB product ID and vendor ID by bootROM in DFU mode. 128 bits are used for secure key used by BootROM to load secure images.1 Programmable at the customer production line. Random read access via sixteen 32-bit registers. Flexible read protection mechanism to hide security related data. Flexible write protection mechanism.
6.23 Serial Peripheral Interface (SPI)

The SPI module is used for synchronous serial data communication with other devices
which support the SPI/SSI protocol. Examples of the devices that this SPI module can
communicate with are memories, camera and WiFi-g. On the LPC3141 secure boot is not supported hence these bits are also available for customer use.
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Low-cost, low-power ARM926EJ microcontrollers

The SPI/SSI-bus is a 5-wire interface, and it is suitable for low, medium, and high data
rate transfers.
This module has the following features: Supports Motorola SPI frame format with a word size of 8/16 bits. Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size
of 4 bit to 16 bit. Receive FIFO and transmit FIFO of 64 half-words each. Serial clock rate master mode maximum 45 MHz. Serial clock rate slave mode maximum 25 MHz. Support for single data access DMA. Full-duplex operation. Supports up to three slaves. Supports maskable interrupts. Supports DMA transfers.
6.24 Universal Asynchronous Receiver Transmitter (UART)

The UART module supports the industry standard serial interface.
This module has the following features: Programmable baud rate with a maximum of 1049 kBd. Programmable data length (5 bit to 8 bit). Implements only asynchronous UART. Transmit break character length indication. Programmable 1 to 2 stops bits in transmission. Odd/Even/Force parity check/generation. Frame error, overrun error and break detection. Automatic hardware flow control. Independent control of transmit, receive, line status, data set interrupts, and FIFOs. SIR-IrDA encoder/decoder (from 2400 to 115 kBd). Supports maskable interrupts. Supports DMA transfers.
6.25 Pulse Code Modulation (PCM) interface

The PCM interface supports the PCM and IOM interfaces.
This module has the following features: Four-wire serial interface. Can function in both Master and Slave modes. Supports: PCM: Pulse code modulation. Single clocking physical format.
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Low-cost, low-power ARM926EJ microcontrollers
MP PCM: Multi-Protocol PCM. Configurable directional per slot. IOM-2: Extended ISDN-Oriented modular. Double clocking physical format. Twelve 8-bit slots in a frame with enabling control per slot. Internal frame clock generation in master mode. Receive and transmit DMA handshaking using a request/clear protocol. Interrupt generation per frame.
PCM (Pulse Code Modulation) is a very common method used for transmitting analog
data in digital format. Most common applications of PCM are Digital audio as in Audio CD
and computers, digital telephony and digital videos.
The IOM (ISDN Oriented Modular) interface is primarily used to interconnect
telecommunications ICs providing ISDN compatibility. It delivers a symmetrical full-duplex
communication link containing user data, control/programming lines, and status channels.
6.26 LCD interface

The dedicated LCD interface contains logic to interface to a 6800 (Motorola) or a 8080
(Intel) compatible LCD controller which support 4/8/16 bit modes. This module also
supports a serial interface mode. The speed of the interface can be adjusted in software to
match the speed of the connected LCD display.
This module has the following features: 4/8/16 bit parallel interface mode: 6800-series, 8080-series. Serial interface mode. Supports multiple frequencies for the 6800/8080 bus to support high- and low-speed
controllers. Supports polling the busy flag from LCD controller to off-load the CPU from polling. Contains a 16 byte FIFO for sending control and data information to the LCD
controller. Supports maskable interrupts. Supports DMA transfers.
6.27I2 C-bus master/slave interface

The LPC3141/3143 contains two I2 C master/slave interfaces.
This module has the following features: I2C0 interface: The I2 C0-bus interface is a standard I2 C-compliant bus interface with
open-drain pins. This interface supports functions described in the I2 C-bus
specification for speeds up to 400 kHz. This includes multi-master operation and
allows powering off this device in a working system while leaving the I2 C-bus
functional. I2C1 interface: The I2 C1-bus interface uses standard I/O pins and is intended for use
with a single-master I2 C-bus and does not support powering off this device. Standard
I/Os also do not support multi-master I2 C implementations. Supports normal mode (100 kHz SCL).
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
Fast mode (400 kHz SCLwith 24 MHz APB clock; 325 kHz with12 MHz APB clock;
175 kHz with 6 MHz APB clock). Interrupt support. Supports DMA transfers (single). Four modes of operation: Master transmitter Master receiver Slave transmitter Slave receiver
6.28 LCD/NAND flash/SDRAM multiplexing

The LPC3141/3143 contains a rich set of specialized hardware interfaces, but the TFBGA
package does not contain enough pins to allow the use of all signals of all interfaces
simultaneously. Therefore a pin-multiplexing scheme is created, which allows the
selection of the right interface for the application.
Pin multiplexing is enabled between the following interfaces: between the dedicated LCD interface and the external bus interface between the NAND flash controller and the memory card interface between UART and SPI between I2STX_0 output and the PCM interface
The pin interface multiplexing is subdivided into five categories: storage, video, audio,
NAND flash, and UART related pin multiplexing. Each category supports several modes,
which can be selected by programming the corresponding registers in the SysCReg.
6.28.1 Pin connections
Table 10. Pin descriptions of multiplexed pins
Video related pin multiplexing

mLCD_CSB LCD_CSB EBI_NSTCS_0 LCD_CSB — LCD chip select for external LCD controller.
EBI_NSTCS_0 — EBI static memory chip select 0.

mLCD_DB_1 LCD_DB_1 EBI_NSTCS_1 LCD_DB_1 — LCD bidirectional data line 1.
EBI_NSTCS_1 — EBI static memory chip select 1.

mLCD_DB_0 LCD_DB_0 EBI_CLKOUT LCD_DB_0 — LCD bidirectional data line 0.
EBI_CLKOUT — EBI SDRAM clock signal.

mLCD_E_RD LCD_E_RD EBI_CKE LCD_E_RD — LCD enable/read signal.
EBI_CKE — EBI SDRAM clock enable.

mLCD_RS LCD_RS EBI_NDYCS LCD_RS — LCD register select signal.
EBI_NDYCS — EBI SDRAM chip select.

mLCD_RW_WR LCD_RW_WR EBI_DQM_1 LCD_RW_WR — LCD read write/write signal.
EBI_DQM_1 — EBI SDRAM data mask output 1.

mLCD_DB_2 LCD_DB_2 EBI_A_2 LCD_DB_2 — LCD bidirectional data line 2.
EBI_A_2 — EBI address line 2.
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Low-cost, low-power ARM926EJ microcontrollers

mLCD_DB_3 LCD_DB_3 EBI_A_3 LCD_DB_3 — LCD bidirectional data line 3.
EBI_A_3 — EBI address line 3.

mLCD_DB_4 LCD_DB_4 EBI_A_4 LCD_DB_4 — LCD bidirectional data line 4.
EBI_A_4 — EBI address line 4.

mLCD_DB_5 LCD_DB_5 EBI_A_5 LCD_DB_5 — LCD bidirectional data line 5.
EBI_A_5 — EBI address line 5.

mLCD_DB_6 LCD_DB_6 EBI_A_6 LCD_DB_6 — LCD bidirectional data line 6.
EBI_A_6 — EBI address line 6.

mLCD_DB_7 LCD_DB_7 EBI_A_7 LCD_DB_7 — LCD bidirectional data line 7.
EBI_A_7 — EBI address line 7.

mLCD_DB_8 LCD_DB_8 EBI_A_8 LCD_DB_8 — LCD bidirectional data line 8.
EBI_A_8 — EBI address line 8.

mLCD_DB_9 LCD_DB_9 EBI_A_9 LCD_DB_9 — LCD bidirectional data line 9.
EBI_A_9 — EBI address line 9.

mLCD_DB_10 LCD_DB_10 EBI_A_10 LCD_DB_10 — LCD bidirectional data line 10.
EBI_A_10 — EBI address line 10.

mLCD_DB_11 LCD_DB_11 EBI_A_11 LCD_DB_11 — LCD bidirectional data line 11.
EBI_A_11 — EBI address line 11.

mLCD_DB_12 LCD_DB_12 EBI_A_12 LCD_DB_12 — LCD bidirectional data line 12.
EBI_A_12 — EBI address line 12.

mLCD_DB_13 LCD_DB_13 EBI_A_13 LCD_DB_13 — LCD bidirectional data line 13.
EBI_A_13 — EBI address line 13.

mLCD_DB_14 LCD_DB_14 EBI_A_14 LCD_DB_14 — LCD bidirectional data line 14.
EBI_A_14 — EBI address line 14.

mLCD_DB_15 LCD_DB_15 EBI_A_15 LCD_DB_15 — LCD bidirectional data line 15.
EBI_A_15 — EBI address line 15.
Storage related pin multiplexing

mGPIO5 GPIO5 MCI_CLK GPIO5 — General Purpose I/O pin 5.
MCI_CLK — MCI card clock.

mGPIO6 GPIO6 MCI_CMD GPIO_6 — General Purpose I/O pin 6.
MCI_CMD — MCI card command input/output.

mGPIO7 GPIO7 MCI_DAT_0 GPIO7 — General Purpose I/O pin 7.
MCI_DAT_0 — MCI card data input/output line 0.

mGPIO8 GPIO8 MCI_DAT_1 GPIO8 — General Purpose I/O pin 8.
MCI_DAT_1 — MCI card data input/output line 1.

mGPIO9 GPIO9 MCI_DAT_2 GPIO9 — General Purpose I/O pin 9.
MCI_DAT_2 — MCI card data input/output line 2.

mGPIO10 GPIO10 MCI_DAT_3 GPIO10 — General Purpose I/O pin 10.
MCI_DAT_3 — MCI card data input/output line 3.
Table 10. Pin descriptions of multiplexed pins …continued
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers
6.28.2 Multiplexing between LCD and MPMC

The multiplexing between the LCD interface and MPMC allows for the following two
modes of operation: MPMC-mode: SDRAM and bus-based LCD or SRAM LCD-mode: Dedicated LCD interface
The external NAND flash is accessible in both modes.
The block diagram Figure 9 gives a high level overview of the modules in the chip that are
involved in the pin interface multiplexing between the EBI, NAND flash controller, MPMC,
and RAM-based LCD interface.
NAND related pin multiplexing

mNAND_RYBN0 NAND_RYBN0 MCI_DAT_4 NAND_RYBN0 — NAND flash controller Read/Not busy signal 0.
MCI_DAT_4 — MCI card data input/output line 4.

mNAND_RYBN1 NAND_RYBN1 MCI_DAT_5 NAND_RYBN1 — NAND flash controller Read/Not busy signal 1.
MCI_DAT_5 — MCI card data input/output line 5.

mNAND_RYBN2 NAND_RYBN2 MCI_DAT_6 NAND_RYBN2 — NAND flash controller Read/Not busy signal 2
MCI_DAT_6 — MCI card data input/output line 6.

mNAND_RYBN3 NAND_RYBN3 MCI_DAT_7 NAND_RYBN3 — NAND flash controller Read/Not busy signal 3.
MCI_DAT_7 — MCI card data input/output line 7.
Audio related pin multiplexing

mI2STX_DATA0 I2STX_DATA0 PCM_DA I2STX_DATA0 — I2S interface 0 transmit data signal.
PCM_DA — PCM serial data line A.

mI2STX_BCK0 I2STX_BCK0 PCM_FSC I2STX_BCK0 — I2S interface 0 transmit bit clock signal.
PCM_FSC — PCM frame synchronization signal.

mI2STX_WS0 I2STX_WS0 PCM_DCLK I2STX_WS0 — I2S interface 0 transmit word select signal.
PCM_DCLK — PCM data clock output.

mI2STX_CLK0 I2STX_CLK0 PCM_DB I2STX_CLK0 — I2S interface 0 transmit clock signal.
PCM_DB — PCM serial data line B.
UART related pin multiplexing

mUART_CTS_N UART_CTS_N SPI_CS_OUT1 UART_CTS_N — UART modem control Clear-to-send signal.
SPI_CS_OUT1 — SPI chip select out for slave 1 (used in master

mode).
mUART_RTS_N UART_RTS_N SPI_CS_OUT2 UART_RTS_N — UART modem control Request-to-Send signal.
SPI_CS_OUT2 — SPI chip select out for slave 2 (used in master

mode).
Table 10. Pin descriptions of multiplexed pins …continued
NXP Semiconductors LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers

Figure 9 only shows the signals that are involved in pad-muxing, so not all interface
signals are visible.
The EBI unit between the NAND flash interface and the MPMC contains an arbiter that
determines which interface is muxed to the outside world. Both NAND flash and
SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin
arbitration (see Section 6.6).
6.28.3 Supply domains

As is shown in Figure 9 the EBI (NAND flash/MPMC-control/data) is connected to a
different supply domain than the LCD interface. The EBI control and address signals are
muxed with the LCD interface signals and are part of supply domain SUP8. The
SDRAM/SRAM data lines are shared with the NAND flash through the EBI and are part of
supply domain SUP4. Therefore the following rules apply for connecting memories: SDRAM and bus-based LCD or SRAM: This is the MPMC mode. The supply voltage
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