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LNBK20D2STN/a3202avaiLNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE)
LNBK20D2-TR |LNBK20D2TRSTN/a2500avaiLNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE)


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LNBK20D2-LNBK20D2-TR
LNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE)
1/14July 2003 COMPLETE INTERFACE FOR TWO LNBs
REMOTE SUPPLY AND CONTROL GUARANTEED 400mA OUTPUT CURRENT LNB SELECTION AND STAND-BY
FUNCTION BUILT-IN TONE OSCILLATOR FACTORY
TRIMMED AT 22KHz FAST OSCILLATOR START-UP FACILITATES
DiSEqC ENCODING TWO SUPPLY INPUTS FOR LOWEST
DISSIPATION BYPASS FUNCTION FOR SLAVE
OPERATION LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC AUXILIARY MODULATION INPUT EXTENDS
FLEXIBILITY CABLE LENGTH COMPENSATION INTERNAL OVER TEMPERATURE
PROTECTION BACKWARD CURRENT PROTECTION COST-EFFECTIVE VERSION OF LNBP
SERIES
DESCRIPTION

Intended for analog and digital satellite receivers,
the LNBK20D2isa monolithic linear voltage
regulator, assembled in SO-20, specifically
designedto provide the powering voltages and the
interfacing signals to the LNB downconverter
situatedin the antenna via the coaxial cable.It has
the same functionality of the LNBP1X and
LNBP20 series, ata reduced output current
capability. Since most satellite receivers have two
antenna ports, the output voltageof the regulator availableat oneof two logic-selectable output
pins (LNBA, LNBB). When theICis powered and
putin Stand-by (EN pin LOW), both regulator
outputs are disabled to allow the antenna
downconverters to be supplied/controlled by
others satellite receivers sharing the same coaxial
lines.In this occurrence the device will limitat3 (max) the backward current that could flow
from LNBA and LNBB output pinsto GND.
For slave operationin single dish, dual receiver
systems, the bypass functionis implemented by electronic switch between the Master Input pin
(MI) and the LNBA pin, thus leaving all LNB
powering and control functions to the Master
Receiver. This electronic switchis closed when
the deviceis powered and EN pinis LOW.
The regulator outputs canbe logic controlledtobeor 18V (typ.) by meanof the VSEL pin for
remote controlling of LNBs. Additionally,itis
possibleto increment by 1V (typ.) the selected
voltage valueto compensate the excess voltage
drop along the coaxial cable (LLC pin HIGH). orderto reduce the power dissipationof the
device when the lowest output voltageis selected,
the regulator has two Supply Input pinsV CC1 and CC2. They mustbe powered respectivelyat 16V
(min) and 23V (min), and an internal switch
automatically will select the suitable supply pin
according to the selected output voltage.If
adequate heatsinkis provided and higher power
losses are acceptable, both supply pins can be
powered by the same 23V source without
affecting any other circuit performance.
The ENT (Tone Enable) pin activates the internal
oscillatorso that the DC outputis modulatedbya
±0.3V, 22KHz (typ.) square wave. This internal
oscillatoris factory trimmed withina toleranceof
±2KHz, thus no further adjustments neither
external components are required. burst coding of the 22KHz tone can be
accomplished thanksto the fast responseof the
ENT input and the prompt oscillator start-up. This
helps designers who want to implement the
DiSEqC protocols (*). orderto improve design flexibility andto allow
implementationof newcoming LNB remote control
standards, an analogic modulation input pinis
LNBK20D2

LNB SUPPLY AND CONTROL VOLTAGE
REGULATOR (PARALLEL INTERFACE)
LNBK20D2
2/14
available (EXTM). An appropriate DC blocking
capacitor must be usedto couple the modulating
signal sourceto the EXTM pin. When external
modulationis not used, the relevant pin canbe left
open.
Two pins are dedicated to the overcurrent
protection/monitoring: CEXT and OLF. The
overcurrent protection circuit works dynamically: soonasan overloadis detectedin either LNB
output, the outputis shut-down fora time Toff
determined by the capacitor connected between
CEXT and GND. Simultaneously the OLF pin, that an open collector diagnostic output flag, from
HIGH IMPEDANCE state goes LOW.
After the time has elapsed, the outputis resumed
fora timeton =1/15toff (typ.) and OLF goesin HIGH
IMPEDANCE.If the overloadis still present, the
protection circuit will cycle again throughtoff and
ton until the overloadis removed. Typical ton+toff
valueis 1200ms whena 4.7μF external capacitor used.
This dynamic operation can greatly reduce the
power dissipationin short circuit condition, still
ensuring excellent power-on start up even with
highly capacitive loadson LNB outputs.
The device is packaged in Multiwatt15 for
thru-holes mounting and in PowerSO-20 for
surface mounting. Whena limited functionalityina
smaller package matches design needs,a range cost-effective PowerSO-10 solutionsis also
offered. All versions have built-in thermal
protection against overheating damage.
(*): External componentsare neededto complyto level2.x and above (bidirectiona) DiSEqCbus hardware requirements. DiSEqCisa
trademarkor EUTELSAT.
PIN CONFIGURATION
(top view)
LNBK20D2
3/14
TABLEA: PIN CONFIGURATIONS

NOTE:the limitedpin availabilityofthe PowerSO-10 package leadsto drop some functions.
ABSOLUTE MAXIMUM RATINGS

AbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under these conditionis
not implied.
THERMAL DATA
LNBK20D2
4/14
LOGIC CONTROLS TRUTH TABLE

NOTE:All logic input pins have internal pull-down resistor (typ.= 250KΩ)
BLOCK DIAGRAM
LNBK20D2
5/14
ELECTRICAL CHARACTERISTICS FOR LNBK SERIES
(TJ=0to 85°C,CI =0.22μF,CO =0.1μF,
EN=H,ENT=L,LLC=L,VIN1=16V, VIN2=23V IOUT=50mA, unless otherwise specified.)
LNBK20D2
6/14
TYPICAL CHARACTERISTICS
(unless otherwise specifiedTj= 25°C)
Figure1:
Output Voltagevs Output Current
Figure2:
Tone Duty Cyclevs Temperature
Figure3:
Tone Fall Timevs Temperature
Figure4:
Tone Frequencyvs Temperature
Figure5:
Tone Rise Timevs Temperature
Figure6:
Tone Amplitudevs Temperature
LNBK20D2
7/14
Figure7:
S.V.R.vs Frequency
Figure8:
External Modulationvs Temperature
Figure9:
Bypass Switch Dropvs Output Current
Figure10:
LNBA External Modulation gainvs
Frequency
Figure11:
Bypass switch Dropvs Output
Current
Figure12:
overload Flag pin Logic LOWvs Flag
Current
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