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LNBH23LQTR
LNB supply and control IC with step-up and I2C interface
November 2010 Doc ID 15335 Rev 4 1/25
LNBH23LLNB supply and control IC with step-up and I²C interface
Features Complete interface between LNB and I²C bus Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @ 0.5 Selectable output current limit by external
resistor Compliant with main satellite receivers output
voltage specification Auxiliary modulation input (EXTM pin)
facilitates DiSEqC™ 1.X encoding Accurate built-in 22 kHz tone generator suits
widely accepted standards Low-drop post regulator and high efficiency
step-up PWM with integrated power NMOS
allow low power losses Overload and over-temperature internal
protections with I²C diagnostic bits LNB short circuit dynamic protection ± 4 kV ESD tolerant on output power pins
Applications STB satellite receivers TV satellite receivers PC card satellite receivers
DescriptionIntended for analog and digital satellite receivers,
the LNBH23L is a monolithic voltage regulator
and interface IC, assembled in QFN32 5 x 5
specifically designed to provide the 13 / 18 V
power supply and the 22 kHz tone signalling to
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
Table 1. Device summary
Contents LNBH23L2/25 Doc ID 15335 Rev 4
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 DiSEqC™ 1.X implementation by EXTM pin . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 DiSEqC™ 1.X implementation with VOTX and EXTM pin connection . . . . 5
2.4 PDC optional circuit for DiSEQC™ 1.X applications using VOTX
signal on to EXTM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 6
2.9 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 T ransmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LNBH23L software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 T ransmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17
LNBH23L ContentsDoc ID 15335 Rev 4 3/25
7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7 DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block diagram LNBH23L
4/25 Doc ID 15335 Rev 4
1 Block diagram
Figure 1. Block diagram
LNBH23L Application information
Doc ID 15335 Rev 4 5/25
2 Application information
This IC has a built-in DC-DC step-up converter that, from a single source from 8 V to 15 V,
generates the voltages (VUP) that let the linear post-regulator to work at a minimum
dissipated power of 0.55 W typ. @ 500 mA load (the linear post-regulator drop voltage is
internally kept at VUP - VOUT = 1.1 V typ.). An under voltage lockout circuit will disable the
whole circuit when the supplied VCC drops below a fixed threshold (6.7 V typically).
Note: In this document the VOUT is intended as the voltage present at the linear post-regulator
output (VoRX pin).
2.1 DiSEqC™ data encoding
The internal 22 kHz tone generator is factory trimmed in accordance to the standards, and
can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin
(DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the
22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) The
TTX function must be disabled setting TTX to LOW. Besides the internal 22 kHz tone
generator, the auxiliary modulation pin (EXTM) can be driven by an external 22 kHz source
and in this case TTX must be set to low.
2.2 DiSEqC™ 1.X implementation by EXTM pin
In order to improve design flexibility and reduce the total application cost, an analogic
modulation input pin is available (EXTM) to generate the 22 kHz tone superimposed to the
VoRX DC output voltage. An appropriate DC blocking capacitor must be used to couple the
modulating signal source to the EXTM pin. If the EXTM solution is used the output R-L filter
can be removed (see Figure 5) saving the external components cost. If this configuration is
used keep TTX set to low.
The pin EXTM modulates the VoRX voltage through the series decoupling capacitor, so that:
VoRX(AC) = VEXTM(AC) x GEXTM
Where VoRX(AC) and VEXTM(AC) are, respectively, the peak to peak voltage on the VoRX and
EXTM pins while GEXTM is the voltage gain from EXTM to VoRX.
2.3 DiSEqC™ 1.X implementation with V OTX and EXTM pin
connection
If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz
tone generator signal available through the VoTX pin to drive the EXTM pin. The VoTX pin
internal circuit must be preventively set ON by setting the TTX function to High. This can be
controlled both through the TTX pin or by I²C bit. By this way the VoTX 22 kHz signal will be
superimposed to the VoRX DC voltage to generate the LNB output 22 kHz tone (see
Figure 3). After TTX is set to High the internal 22 kHz tone generator available through the
VoTX pin can be activated during the 22 kHz transmission either by DSQIN pin or by the TEN
bit.The DSQIN internal circuit activates the 22 kHz tone on the VoTX output with 0.5 cycles ±
25 µs delay from the TTL signal presence on the DSQIN pin, and it stops with 1 cycles ± 25
µs delay after the TTL signal is expired. As soon as the tone transmission is expired, the
Application information LNBH23L
6/25 Doc ID 15335 Rev 4
VoTX internal circuits must be disabled by setting the TTX to LOW. The 13 / 18 V power
supply will be always provided to the LNB from the VoRX pin.
2.4 PDC optional circuit for DiSEQC™ 1.X applications using OTX signal on to EXTM pin
In some applications, at light output current (< 50 mA) having heavy LNB output capacitive
load, the 22 kHz tone can be distorted. In this case it is possible to add the "Optional"
external components shown in the typical application circuits (see Figure 4) connected
between VoRX and PDC pin. This optional circuit acts as an active pull-down discharging the
output capacitance only when the internal 22 kHz tone is activated. This optional circuit is
not needed in standard applications having IOUT > 50 mA and capacitive load up to 250 nF.
2.5 I²C interface
The main functions of the IC are controlled via I²C bus by writing 6 bits on the system
register (SR 8 bits in write mode). On the same register there are 5 bits that can be read
back (SR 8 bits in read mode) to provide the diagnostic flags of two internal monitoring
functions (OTF, OLF) and three output voltage register status (EN, VSEL, LLC) received by
the IC (see below diagnostic functions section). In read mode there are 3 T est bits (test 1 - 2
- 3) that must be disregarded from the MCU. While, in write mode, 2 test bits (test 4 - 5) must
be always set LOW.
2.6 Output voltage selection
When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the VSEL bit (voltage SELect). Additionally, the LNBH23L is provided
with the LLC I²C bit that increases the selected voltage value to compensate possible
voltage drop along the output line. The LNBH23L is also compliant to the USA LNB power
supply standards. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must
be set LOW (if the TTX pin is not used it can be left floating or to GND but the TTX bit must
be set LOW during the stand-by condition).
2.7 Diagnostic and protection functions
The LNBH23L has two diagnostic internal functions provided via I²C bus by reading 2 bits on
the system register (SR bits in read mode). the diagnostic bits are, in normal operation (no
failure detected), set to LOW. The diagnostic bits are dedicated to the over-temperature and
over-load protections status (OTF and OLF).
2.8 Over-current and short circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short circuit condition,
the device is provided with a dynamic short circuit protection. It is possible to set the short
circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current
protection circuit works dynamically: as soon as an overload is detected, the output is shut-
LNBH23L Application information
Doc ID 15335 Rev 4 7/25
down for a time TOFF , typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the
system register is set to "1". After this time has elapsed, the output is resumed for a time
TON = 1/10 TOFF = 90 ms (typ.). At the end of TON, if the overload is still detected, the
protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no
overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to
LOW. Typical TON + TOFF time is 990ms and an internal timer determines it. This dynamic
operation can greatly reduce the power dissipation in short circuit condition, still ensuring
excellent power-on start-up in most conditions. However, there could be some cases in
which a highly capacitive load on the output may cause a difficult start-up when the dynamic
protection is chosen. This can be solved by initiating any power start-up in static mode (PCL
= 1) and, then, switching to the dynamic mode (PCL = 0) after a chosen amount of time
depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to
"1" when the current clamp limit is reached and returns LOW when the overload condition is
cleared.
2.9 Thermal protection and diagnostic
The LNBH23L is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the
diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to
LOW when the junction is cooled down to 135 °C (typ.)
2.10 Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
ISEL pin. The resistor value defines the output current limit by the equation:
IMAX (A) = 10000 / RSEL
where RSEL is the resistor connected between ISEL and GND. The highest selectable current
limit threshold shall be 0.65 A typ with RSEL = 15 kΩ. The above equation defines the typical
threshold value.
Note: External components are needed to comply DiSEqC™ bus hardware requirements. Full
compliance of the whole application with DiSEqC™ specifications is not implied by the bare
use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.
Pin configuration LNBH23L
8/25 Doc ID 15335 Rev 4 Pin configuration
Figure 2. Pin connections (bottom view)
Table 2. Pin description
LNBH23L Pin configuration
Doc ID 15335 Rev 4 9/25
Table 2. Pin description (continued)
Maximum ratings LNBH23L
10/25 Doc ID 15335 Rev 4
4 Maximum ratings
Table 3. Absolute maximum ratings (1) Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or
voltage sources may cause permanent damage to the device.
Table 4. Thermal data
LNBH23L Typical application circuit
Doc ID 15335 Rev 4 11/25
Typical application circuit
Figure 3. DiSEqC 1.x using internal 22 kHz tone generator
Figure 4. DiSEqC 1.x using internal 22 kHz tone generator and "optional" PDC circuit
Typical application circuit LNBH23L
12/25 Doc ID 15335 Rev 4
Figure 5. DiSEqC 1.x using external 22 kHz tone generator source through EXTM pin
Table 5. BOM list These components can be added to avoid any 22 kHz tone distortion due to heavy capacitive output loads. If not needed
they can be removed leaving the PDC pin floating.
LNBH23L Typical application circuit
Doc ID 15335 Rev 4 13/25
o calculate the boost converter peak current (IPEAK) of L1, use the following formula:
Equation 1
