LNBH23 ,LNBs supply and control IC with step-up and I2C interfaceBlock diagram . . . . . . 32 Application information . . . . . . 42.1 DiSEqC™ data encod ..
LNBH23LQTR ,LNB supply and control IC with step-up and I2C interfaceFeatures■ Complete interface between LNB and I²C bus■ Built-in DC-DC converter for single 12 V supp ..
LNBH23PPR ,LNBs supply and control IC with step-up and I2C interfaceBlock diagram IISEL SEL TT TTX X SD SDA A S SCL CL Vc Vc Vcc c c By By Byp p p V V Vcc- cc- ..
LNBH23PPR ,LNBs supply and control IC with step-up and I2C interfaceFeatures■ Complete interface between LNB and I²C bus■ Built-in DC-DC converter for single 12 V supp ..
LNBH23QTR ,LNBs supply and control IC with step-up and I2C interfaceFeatures■ Complete interface between LNB and I²C bus■ Built-in DC-DC converter for single 12 V supp ..
LNBH24 ,Dual LNB supply and control IC with step-up and I2C interfaceBlock diagram TT TTX X- - - -A A ISE ISEL L- - - -A A ADDR ADDR - - - -A A SDA SDA S SC CL ..
LRG6SP , Advanced Power TOPLED Enhanced ThinFilm LED Lead (Pb) Free Product - RoHS Compliant
LRMS-1W ,Circuits - Surface Mount Frequency Mixer
LRMS-1W ,Circuits - Surface Mount Frequency Mixer
LRPS-2-11+ ,Circuits - Power Splitter/Combiner
LRS1302 , Stacked Chip 8M Flash and 1M SRAM
LRS1329 , Stacked Chip 16M Flash and 2M SRAM
LNBH23-LNBH23QTR
LNBs supply and control IC with step-up and I2C interface
February 2013 Doc ID 13356 Rev 8 1/32
LNBH23LNBs supply and control IC with step-up and I²C interface
Datasheet − production data
Features Complete interface between LNB and I²C bus Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @ 0.75
A), with integrated NMOS Selectable output current limit by external
resistor Compliant with main satellite receiver systems
specifications New accurate built-in 22 kHz tone generator
suits widely accepted standards (patent
pending) Fast oscillator start-up facilitates DiSEqC™
encoding Built-in 22 kHz tone detector supports bi-
directional DiSEqC™ 2.0 Very low-drop post regulator and high
efficiency step-up PWM with integrated power
NMOS allow low power losses Two output pins suitable to by-pass the output
R-L filter and avoid any tone distortion (R-L
filter as per DiSEqC™ 2.0 specs, see typ.
application circuits) Overload and over-temperature internal
protections with I²C diagnostic bits Output voltage and output current level
diagnostic feedback by I²C bits LNB short circuit dynamic protection ± 4 kV ESD tolerant on output power pins
DescriptionIntended for analog and digital satellite
receivers/sat-TV, sat-PC cards, the LNBH23 is a
monolithic voltage regulator and interface IC,
assembled in PowerSSO-24 eP AD and QFN32 (5
x 5 mm.) ePAD, specifically designed to provide
the 13/18 V power supply and the 22 kHz tone
signalling to the LNB down-converter in the
antenna dish or to the multi-switch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I²C
standard interfacing.
Table 1. Device summary
Contents LNBH232/32 Doc ID 13356 Rev 8
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Data encoding by external tone generator (EXTM) . . . . . . . . . . . . . . . . . . 5
2.5 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Output voltage diagnostic - VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.9 22 kHz tone diagnostic - TMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.10 Minimum output current diagnostic - IMON . . . . . . . . . . . . . . . . . . . . . . . . 6
2.11 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.12 Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 7
2.13 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LNBH23 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LNBH23 ContentsDoc ID 13356 Rev 8 3/32
7.3 Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7 DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Block diagram LNBH23
4/32 Doc ID 13356 Rev 8
1 Block diagram
Figure 1. Block diagram
LNBH23 Application information
Doc ID 13356 Rev 8 5/32
2 Application information
This IC has a built-in DC-DC step-up converter with integrated NMOS that, from a single
source from 8 V to 15 V, generates the voltages (VUP) that let the linear post-regulator to
work at a minimum dissipated power of 0.375 W T yp. @ 500 mA load (the linear post-
regulator drop voltage is internally kept at VUP-VORX=0.75 V typ.). An under voltage lockout
circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7
V typically).
Note: In this document the output voltage (VO) is intended as the voltage present at the linear
post-regulator output (VORX pin).
2.1 DiSEqC™ data encoding and decoding
The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance
to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by
a dedicated pin (DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN
I²C bit in case the 22 kHz presence is requested in continuous mode. In stand-by condition
(EN bit LOW) The TTX function must be disabled setting TTX to LOW.
2.2 DiSEqC™ 2.0 implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing
(see Note 1). It’s input pin (DETIN) must be AC coupled to the DiSEqC™ BUS, and
extracted PWK data are available on the DSQOUT pin. To comply to the bi-directional
DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH23 is
provided with two output pins, one for the dc voltage output (VoRX) and one for the 22 kHz
tone transmission (VoTX). The VoTX must be activated only during the tone transmission
while the VoRX provides the 13/18 V output voltage. This allows the 22 kHz Tone to pass
without any losses due to the R-L filter impedance (see Figure 4 typ. application circuit).
During the 22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by
the TEN bit, the VoTX pin must be preventively set ON by the TTX function. This can be
controlled both through the TTX pin and by I²C bit. As soon as the tone transmission is
expired, the VoTX must be disabled by setting the TTX to LOW to set the device in the 22
kHz receiving mode. The 13/18 V power supply is always provided to the LNB from the VoRX
pin through the R-L filter.
2.3 DiSEqC™ 1.X implementation
When the LNBH23 is used in DiSEqC™ 1.x applications the R-L filter is always needed for
the proper operation of the new 22 kHz tone generator (patent pending. See application
circuit). Also in this case, the TTX function must be preventively enabled before to start the
22 kHz data transmission and disabled as soon as the data transmission has been expired.
The tone can be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal
circuit activates the 22 kHz tone on the VoTX output with 0.5 cycles ±25 µs delay from the
TTL signal presence on the DSQIN pin, and it stops with 1 cycles ±25 µs delay after the TTL
signal is expired.
Application information LNBH23
6/32 Doc ID 13356 Rev 8
2.4 Data encoding by external tone generator (EXTM)
In order to improve design flexibility an external tone input pin is available (EXTM). The
EXTM is a logic input pin which activates the 22 kHz tone output, on the VoTX pin, by using
the LNBH23 integrated tone generator (similarly to the DSQIN pin function). As a matter of
fact, the output tone waveform characteristics will be always internally controlled by the
LNBH23 tone generator and the EXTM signal will be used just as a timing control of the
DiSEqC tone data encoding on the VoTX output. A TTL compatible 22 kHz signal is required
for the proper control of the EXTM pin function. Before to send the TTL signal on the EXTM
pin, the VoTX tone generator must be previously enabled through the TTX function (TTX pin
or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal
code, it activates the 22 kHz tone on the VoTX output with 1.5 cycles ±25 µs delay from the
TTL signal presence on the EXTM pin, and it stops with 2 cycles ±25 µs delay after the TTL
signal is expired. Refer to the below Figure2.
Figure 2. EXTM waveform
2.5 I²C interface
The main functions of the IC are controlled via I²C bus by writing 8 bits on the system
register (SR 8 bits in write mode). On the same register there are 8 bits that can be read
back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the
diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF , OLF)
while, three will report the last output voltage register status (EN, VSEL, LLC) received by
the IC (see below diagnostic functions section).
2.6 Output voltage selection
When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the V SEL bit (Voltage SELect) for remote controlling of non-DiSEqC
LNBs. Additionally, the LNBH23 is provided with the LLC I²C bit that increases the selected
voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.
The LNBH23 is also compliant to the USA LNB power supply standards. In order to allow
fast transition of the output voltage from 18 V to 13 V and vice versa, the LNBH23 is
provided with the VCTRL TTL pin which keeps the output to 13 V when it is set LOW and to
18 V when it is set HIGH or floating. V SEL and, if required, LLC bits must be set HIGH before
to use the VCTRL pin to switch the output voltage level. If VCTRL=1 or floating V oRX =18.5 V
(or 19.5 V if LLC=1). With VCTRL=0 V oRX =13.4 V (LLC= either 0 or 1). Be aware that the
VCTRL pin controls only the linear regulator V oRX stage while the step-up VUP voltage is
controlled only through the VSEL and LLC I²C bits, that is: Even if VCTRL=0 (keeping oRX =13.4 V) you will have VUP =19.25 V typ when V SEL =1 and 20.25 V with V SEL =LLC=1.
LNBH23 Application information
Doc ID 13356 Rev 8 7/32
This means that VCTRL=0 must be used only for short time to avoid the higher power
dissipation. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set
LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during
the stand-by condition).
2.7 Diagnostic and protection functions
The LNBH23 has 5 diagnostic internal functions provided via I²C bus by reading 5 bits on
the system register (SR bits in read mode). All the diagnostic bits are, in normal operation
(no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature
and over-load protections status (OTF and OLF) while, the remaining 3 bits, are dedicated to
the output voltage level (VMON), 22 kHz tone (TMON) and to the minimum load current
diagnostic function (IMON).
2.8 Output voltage diagnostic - VMON
When VSEL=0 or 1 and LLC=0, the output voltage pin (VoRX) is internally monitored and, as
long as the output voltage level is below the guaranteed limits the VMON I²C bit is set to "1".
The output voltage diagnostic is valid only with LLC=0. Any VMON information with LLC=1
must be disregarded by the MCU.
2.9 22 kHz tone diagnostic - TMON
The 22 kHz tone can be internally detected and monitored if DETIN pin is connected to the
LNB output bus (see typical application circuits Figure 4) through a decoupling capacitor.
The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz T one amplitude
and/or the tone frequency is out of the guaranteed limits (see TMON limits in the electrical
characteristics Table 13), the TMON I²C bit is set to "1".
2.10 Minimum output current diagnostic - IMON
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH23 is provided with a minimum output current flag by the
IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA
typically with ITEST=1 and 6 mA with ITEST=0. The minimum current diagnostic function
(IMON) is always active. In order to make it work even in a multi-IRD configuration (multi-
switch), where the supply current could be sunk only from the higher supply voltage
connected to the multi-switch box, the LNBH23 is provided with the AUX I²C bit which can
be set HIGH, in write mode by the MCU, before to read the IMON I²C bit status, to force the
LNBH23 output voltage as the highest voltage on the bus (22 V typ.) during the minimum
current diagnostic phase. When the AUX bit is set to HIGH, the VoRX is set to 22 V (typ.) and
VUP is set to 22.75 V (VUP = VoRX+0.75 V typ.) independently of the VSEL/LLC bits status. If
the AUX function is used to force the VoRX to 22 V , it is recommended to set the AUX bit to
LOW as soon as the minimum current test phase is expired, so that the VoRX voltage will be
controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the
IMON function must be used only with the 22 kHz tone transmission deactivated
(TEN=TTX=0 and DSQIN=LOW), otherwise the IMON bit could be erroneously set to 0 even
if the output current is below the minimum current thresholds (6 mA or 12 mA). Any TMON
information with 22 kHz tone enabled must be disregarded by the MCU.
Application information LNBH23
8/32 Doc ID 13356 Rev 8
2.11 Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
ISEL pin. The resistor value defines the output current limit by the equation:
IMAX[A] = 10000/RSEL
where RSEL is the resistor connected between ISEL and GND. The highest selectable current
limit threshold is 1.0 A typ with RSEL=10 kΩ. The above equation defines the typical
threshold value.
2.12 Over-current and short circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short circuit condition,
the device is provided with a dynamic short circuit protection. It is possible to set the short
circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current
protection circuit works dynamically: as soon as an overload is detected, the output current
is provided for 90 ms (typ.), after that the output is set in shut-down for a time TOFF of
typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the system register is set to
"1". After this time has elapsed, the output is resumed for a time TON=1/10 TOFF = 90 ms
(typ.). At the end of TON, if the overload is still detected, the protection circuit will cycle again
through TOFF and TON. At the end of a full TON in which no overload is detected, normal
operation is resumed and the OLF diagnostic bit is reset to LOW. Typical TON +TOFF time is
990 ms and an internal timer determines it. This dynamic operation can greatly reduce the
power dissipation in short circuit condition, still ensuring excellent power-on start-up in most
conditions. However, there could be some cases in which a highly capacitive load on the
output may cause a difficult start-up when the dynamic protection is chosen. This can be
solved by initiating any power start-up in static mode (PCL=1) and, then, switching to the
dynamic mode (PCL=0) after a chosen amount of time depending on the output
capacitance. Also in static mode, the diagnostic OLF bit goes to "1" when the current clamp
limit is reached and returns LOW when the overload condition is cleared.
2.13 Thermal protection and diagnostic
The LNBH23 is also protected against overheating: when the junction temperature exceeds
150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic
OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when
the junction is cooled down to 135 °C (typ.).
Note: 1 External components are needed to comply to bidirectional DiSEqC™ bus hardware
requirements. Full compliance of the whole application with DiSEqC™ specifications is not
implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT. I²C is
trademark of Philips Semiconductors.
LNBH23 Pin configuration
Doc ID 13356 Rev 8 9/32
3 Pin configuration
Figure 3. Pin connections (top view for PowerSSO-24, bottom view for QFN32)
Table 2. Pin description
Pin configuration LNBH23
10/32 Doc ID 13356 Rev 8
Table 2. Pin description (continued)
LNBH23 Maximum ratings
Doc ID 13356 Rev 8 11/32
4 Maximum ratings
Note: 1 Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent damage to the device.
Table 3. Absolute maximum ratings
Table 4. Thermal data
Application circuit LNBH23
12/32 Doc ID 13356 Rev 8
5 Application circuit
Figure 4. Typical application circuit
Table 5. Bill of material
LNBH23 Application circuit
Doc ID 13356 Rev 8 13/32
To calculate the boost converter peak current (IPEAK) of L1, use the following formula:
Equation 1
Table 5. Bill of material (continued)
I²C bus interface LNBH23
14/32 Doc ID 13356 Rev 8 I²C bus interface
Data transmission from main MCU to the LNBH23 and vice versa takes place through the 2
wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
6.1 Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
6.2 Start and stop condition
As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each ST ART condition.
6.3 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4 Acknowledge
The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7). The peripheral (LNBH23) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH23 won't generate acknowledge if the
VCC supply is below the under voltage lockout threshold (6.7 V typ.).
6.5 Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH23, the MCU can use a simpler
transmission: simply it waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.
LNBH23 I²C bus interface
Doc ID 13356 Rev 8 15/32
Figure 5. Data validity on the I²C bus
Figure 6. Timing diagram of I²C bus
Figure 7. Acknowledge on the I²C bus
LNBH23 software description LNBH23
16/32 Doc ID 13356 Rev 8 LNBH23 software description
7.1 Interface protocol
The interface protocol comprises: A start condition (S) A chip address byte (the LSB bit determines read(=1)/write(=0) transmission) A sequence of data (1 byte + acknowledge) A stop condition (P)
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, two selectable addresses available through ADDR pin (see Address pin
characteristics Table 10)
7.2 System register (SR, 1 byte)
Write = control bits functions in write mode
Read= diagnostic bits in read mode.
All bits reset to 0 at power On
7.3 Transmitted data (I²C bus write mode)
When the R/W bit in the chip address is set to 0, the main MCU can write on the system
register (SR) of the LNBH23 via I²C bus. All and 8 bits are available and can be written by
the MCU to control the device functions as per the below truth table.
