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LMH0341SQ/NOPB |LMH0341SQNOPBNSCN/a160avai3Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface 48-WQFN -40 to 85


LMH0341SQ/NOPB ,3Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface 48-WQFN -40 to 85FEATURES DESCRIPTIONThe LMH0341/0041/0071/0051 SDI Deserializers are23• 5-Bit LVDS Interfacepart of ..
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LMH0341SQ/NOPB
3Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface
CDR
Control
LVDS Drivers
CLK
Data
LOCK
RESET
RX4
RX2
RX1
l to
Pa
lle
l 1
Byp
ssa
GPIO[2:0]
Checkfor Samples: LMH0041, LMH0051, LMH0071, LMH0341
1FEATURES DESCRIPTION

The LMH0341/0041/0071/0051 SDI Deserializers are
23• 5-Bit LVDS Interface
partof TI’s familyof FPGA-Attach SER/DES products• No External VCOor Clock Required supporting 5-bit LVDS interfaces with FPGAs. When Reclocked Serial Loopthrough With Cable paired witha host FPGA the LMH0341 automatically
Driver
detects the incoming data rate and decodes the raw
5-bit data words compliantto anyof the following• Powerdown Mode standards: DVB-ASI, SMPTE 259M, SMPTE 292M,• 3.3V SMBus Configuration Interface or SMPTE 424M. See Table1 for details on which Small 48-Pin WQFN Package Standards are supported per device. Industrial Temperature range: -40°Cto +85°C The interface between the LMH0341 and the host
FPGA consistsofa 5-bit wide LVDS bus, an LVDSAPPLICATIONS clock and an SMBus interface. No external VCOsor
clocks are required. The LMH0341 CDR detects the• SDI Interfaces for: frequency from the incoming data stream, generates– Video Cameras a clean clock and transmits both clock and datato DVRs the host FPGA. The LMH0341, LMH0041 and
LMH0071 includea serial reclocked loopthrough with– Video Switchers integrated SMPTE compliant cable driver. Referto– Video Editing Systems Table1 fora complete listing of single channel
deserializers offeredin this family.KEY SPECIFICATIONS The FPGA-Attach SER/DES product family is• Output compliant with SMPTE 259M-C, SMPTE supported bya suiteofIP292M, SMPTE 424M and DVB-ASI (See Table1) engineerto quickly develop
the SER/DES products. The• Typical power dissipation: 590 mW
physically small48 pin WQFN(loopthrough disabled, 3G datarate) 0.6UI Minimum Input Jitter Tolerance
General Block Diagram
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