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LM3S9B92-IQC80-C5 |LM3S9B92IQC80C5TIN/a1200avaiStellaris LM3S Microcontroller 100-LQFP -40 to 85


LM3S9B92-IQC80-C5 ,Stellaris LM3S Microcontroller 100-LQFP -40 to 85Block Diagram .. 802.2 Overview . 812.2.1 System-Level Interface ........ 812.2.2 Integrated Config ..
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LM3S9B92-IQC80-C5
Stellaris LM3S Microcontroller 100-LQFP -40 to 85
Block Diagram .. 802.2 Overview . 812.2.1 System-Level Interface ........ 812.2.2 Integrated Configurable Debug ..... 812.2.3 Trace Port Interface Unit (TPIU) .... 822.2.4 Cortex-M3 System Component Details ... 822.3 Programming Model ... 832.3.1 Processor Mode and Privilege Levels for Software Execution ....... 832.3.2 Stacks ..... 832.3.3 Register Map .... 842.3.4 Register Descriptions . 852.3.5 Exceptions and Interrupts .... 982.3.6 Data Types ....... 982.4 Memory Model .. 982.4.1 Memory Regions, Types and Attributes . 1002.4.2 Memory System Ordering of Memory Accesses ...... 1012.4.3 Behavior of Memory Accesses .... 1012.4.4 Software Ordering of Memory Accesses ........ 1022.4.5 Bit-Banding ..... 1032.4.6 Data Storage .. 1052.4.7 Synchronization Primitives . 1062.5 Exception Model ...... 1072.5.1 Exception States ...... 1082.5.2 Exception Types ....... 108July03,20143TexasInstruments-ProductionDataTableofContents2.5.3 Exception Handlers .. 1112.5.4 Vector Table .... 1112.5.5 Exception Priorities ... 1122.5.6 Interrupt Priority Grouping .. 1132.5.7 Exception Entry and Return ........ 1132.6 Fault Handling . 1152.6.1 Fault Types ..... 1162.6.2 Fault Escalation and Hard Faults . 1162.6.3 Fault Status Registers and Fault Address Registers 1172.6.4 Lockup .. 1172.7 Power Management . 1172.7.1 Entering Sleep Modes ....... 1182.7.2 Wake Up from Sleep Mode 1182.8 Instruction Set Summary .... 1193Cortex-M3Peripherals........1223.1
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