LIS3LV02DL-TR ,Linear Accelerometer 3-Axis ?g/ ?g with SPI/I2C digital interfaceFeatures■ 2.16 V to 3.6 V single supply operation■ 1.8 V compatible IOs2■ I C/SPI digital output in ..
LK112M15TR ,LOW NOISE LOW DROP VOLTAGE REGULATOR WITH SHUTDOWN FUNCTIONLK112SERIESLOW NOISE LOW DROP VOLTAGE REGULATORWITH SHUTDOWN FUNCTION ■ OUTPUT CURRENT UP TO 150mA ..
LK112M16TR ,LOW NOISE LOW DROP VOLTAGE REGULATOR WITH SHUTDOWN FUNCTIONABSOLUTE MAXIMUM RATINGS Symbol Parameter² Value UnitV DC Input Voltage16 VIV Shutdown Input V ..
LK112M17TR ,LOW NOISE LOW DROP VOLTAGE REGULATOR WITH SHUTDOWN FUNCTIONLK112SERIESLOW NOISE LOW DROP VOLTAGE REGULATORWITH SHUTDOWN FUNCTION ■ OUTPUT CURRENT UP TO 150mA ..
LK112M18TR ,LOW NOISE LOW DROP VOLTAGE REGULATOR WITH SHUTDOWN FUNCTIONLK112SERIESLOW NOISE LOW DROP VOLTAGE REGULATORWITH SHUTDOWN FUNCTION ■ OUTPUT CURRENT UP TO 150mA ..
LK112M21TR ,LOW NOISE LOW DROP VOLTAGE REGULATOR WITH SHUTDOWN FUNCTIONLK112SERIESLOW NOISE LOW DROP VOLTAGE REGULATORWITH SHUTDOWN FUNCTION ■ OUTPUT CURRENT UP TO 150mA ..
LM324AD ,QUAD DIFFERENTIAL INPUT OPERATIONAL AMPLIFIERSstandard operational amplifier types in single supply applications. Thequad amplifier can operate a ..
LM324ADB , QUADRUPLE OPERATIONAL AMPLIFIERS
LM324ADBR ,Quad General Purpose Operational AmplifierMaximum Ratings.. 410 Power Supply Recommendations... 136.2 ESD Ratings ...... 411 Layout.... 136.3 ..
LM324ADR ,Quad General Purpose Operational AmplifierElectrical Characteristics for LMx24A andLM324KA.... 6 12.2 Related Links.. 156.8 Operating Conditi ..
LM324ADR2 ,Single Supply Quad Operational Amplifierstandard operational amplifier types in single supply applications. Thequad amplifier can operate a ..
LM324ADRG4 ,Quadruple Operational Amplifier 14-SOIC 0 to 70Maximum Ratings.. 410 Power Supply Recommendations... 136.2 ESD Ratings ...... 411 Layout.... 136.3 ..
LIS3LV02DL-LIS3LV02DL-TR
Linear Accelerometer 3-Axis ?g/ ?g with SPI/I2C digital interface
January 2008 Rev 2 1/48
LIS3L V02DLMEMS inertial sensor
3-axis - ±2g/±6g digital output low voltage linear accelerometer
Features 2.16 V to 3.6 V single supply operation 1.8 V compatible IOsI2 C/SPI digital output interfaces Programmable 12 or 16 bit data representation Interrupt activated by motion Programmable interrupt threshold Embedded self test High shock survivability ECOPACK® compliant (see Section9)
DescriptionThe LIS3LV02DL is a three axes digital output
linear accelerometer that includes a sensing
element and an IC interface able to take the
information from the sensing element and to
provide the measured acceleration signals to the
external world through an I2 C/SPI serial interface.
The sensing element, capable of detecting the
acceleration, is manufactured using a dedicated
process developed by ST to produce inertial
sensors and actuators in silicon.
The IC interface instead is manufactured using a
CMOS process that allows high level of
integration to design a dedicated circuit which is
factory trimmed to better match the sensing
element characteristics.
The LIS3LV02DL has a user selectable full scale
of ±2g, ±6g and it is capable of measuring
acceleration over a bandwidth of 640 Hz for all
axes. The device bandwidth may be selected
accordingly to the application requirements.
The self-test capability allows the user to check
the functioning of the device.
The device may be also configured to generate an
inertial wake-up/free-fall interrupt signal when a
programmable acceleration threshold is crossed
at least in one of the three axes.
The LIS3LV02DL is available in plastic SMD
package and it is specified over a temperature
range extending from -40°C to +85°C.
The LIS3LV02DL belongs to a family of products
suitable for a variety of applications: Free-Fall detection Motion activated functions in portable
terminals Antitheft systems and Inertial navigation Gaming and virtual reality input devices Vibration monitoring and compensation
Table 1. Device summary
Content LIS3LV02DL2/48
Content Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 LGA-16 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 102.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.2 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5.3 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.1 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.3 SPI Read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIS3LV02DL Content
3/48 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 OFFSET_X (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 OFFSET_Y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 OFFSET_Z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5 GAIN_X (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6 GAIN_Y (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.7 GAIN_Z (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.8 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.9 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.10 CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.11 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.12 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.13 OUTX_L (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.14 OUTX_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.15 OUTY_L (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.16 OUTY_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.17 OUTZ_L (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.18 OUTZ_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.19 FF_WU_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.20 FF_WU_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.21 FF_WU_ACK (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.22 FF_WU_THS_L (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.23 FF_WU_THS_H (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.24 FF_WU_DURATION (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.25 DD_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.26 DD_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.27 DD_ACK (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.28 DD_THSI_L (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.29 DD_THSI_H (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.30 DD_THSE_L (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.31 DD_THSE_H (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Content LIS3LV02DL
4/48 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 Mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.2 Mechanical characteristics derived from measurement in the -40°C to +85°C
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3 Electro-mechanical characteristics at 25°C . . . . . . . . . . . . . . . . . . . . . . . 44
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIS3LV02DL List of figures
5/48
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. LIS3LV02DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Multiple bytes SPI write protocol (2 bytes example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. X-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. X-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. Y-axis zero-g level at 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 15. Y-axis sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16. Z-axis zero-g level at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 17. Z-axis Sensitivity at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18. X-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 19. X-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. Y-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Y-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Z-axis zero-g level change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. Z-axis sensitivity change vs. temperature at 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. X and Y axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 25. Z axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Current consumption in Power-Down mode (Vdd=3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. Current consumption in operational mode (Vdd=3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 28. LGA-16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
List of tables LIS3LV02DL
6/48
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted. . . . . . . . . . . . 5
Table 4. Mechanical characteristics @ Vdd=2.5 V, T=25 °C unless otherwise noted . . . . . . . . . . . . 7
Table 5. Electrical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted . . . . . . . . . . . . . 9
Table 6. SPI Slave Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 18
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18
Table 15. Registers address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Register (0Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Register description (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. Register (16h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Register description (16h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 20. Register (17h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. Register description (17h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22. Register (18h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 23. Register description (18h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 24. Register (19h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 25. Register description (19h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 26. Register (1Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 27. Register description (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 28. Register (1Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 29. Register description (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 30. Register (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 31. Register description (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 32. Register (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 33. Register description (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 34. Register (22h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 35. Register description (22h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 36. Register (27h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 37. Register description (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 38. Register (28h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 39. Register description (28h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 40. Register (29h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 41. Register description (29h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 42. Register (2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 43. Register description (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 44. Register (2Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 45. Register description (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 46. Register (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 47. Register description (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 48. Register (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LIS3LV02DL List of tables
7/48
Table 49. Register description (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 50. Register (30h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 51. Register description (30h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 52. Register (31h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 53. Register description (31h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 54. Register (34h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 55. Register description (34h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 56. Register (35h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 57. Register description (35h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 58. Register (36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 59. Register description (36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 60. Register (38h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 61. Register description (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 62. Register (39h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 63. Register description (39h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 64. Register (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 65. Register description (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 66. Register (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 67. Register description (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 68. Register (3Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 69. Register description (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 70. Register (3Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 71. Register description (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 72. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Block diagram and pin description LIS3LV02DL
8/48 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 LGA-16 pin description
Figure 2. Pin connection
Table 2. Pin description
LIS3LV02DL Block diagram and pin description
9/48
Table 2. Pin description
Mechanical and electrical specifications LIS3LV02DL
10/48 Mechanical and electrical specifications
2.1 Mechanical characteristics
Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted(1)
LIS3LV02DL Mechanical and electrical specifications
11/48 The product is factory calibrated at 3.3 V. The device can be used from 2.16 V to 3.6 V Typical specifications are not guaranteed Verified by wafer level test and specification of initial offset and sensitivity Zero-g level offset value after MSL3 preconditioning Offset can be eliminated by enabling the built-in high pass filter (HPF) Results of accelerated reliability tests Self Test output changes with the power supply. “Self test output change” is defined as OUTPUT[LSb](Self-test bit on
ctrl_reg1=1) - OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=1g/1024 at 12bit representation, 2g Full-Scale Output data reach 99% of final value after 5/ODR when enabling Self-Test mode due to device filtering ODRx is output data rate. Refer to Table 5 for specifications
Table 3. Mechanical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted(1)
(continued)
Mechanical and electrical specifications LIS3LV02DL
12/48
Table 4. Mechanical characteristics @ Vdd=2.5 V , T=25 °C unless otherwise noted(1)
LIS3LV02DL Mechanical and electrical specifications
13/48 The product is factory calibrated at 3.3 V. The device can be used from 2.16 V to 3.6 V Typical specifications are not guaranteed Verified by wafer level test and specification of initial offset and sensitivity Zero-g level offset value after MSL3 preconditioning Offset can be eliminated by enabling the built-in high pass filter (HPF) Results of accelerated reliability tests Self Test output changes with the power supply. “Self test output change” is defined as OUTPUT[LSb](Self-test bit on
ctrl_reg1=1) - OUTPUT[LSb](Self-test bit on ctrl_reg1=0). 1LSb=1g/1024 at 12bit representation, 2g Full-Scale Output data reach 99% of final value after 5/ODR when enabling Self-Test mode due to device filtering ODRx is output data rate. Refer to Table 5 for specifications
Table 4. Mechanical characteristics @ Vdd=2.5 V , T=25 °C unless otherwise noted(1)
(continued)
Mechanical and electrical specifications LIS3LV02DL
14/48
2.2 Electrical characteristics
Table 5. Electrical characteristics @ Vdd=3.3 V, T=25 °C unless otherwise noted (1) The product is factory calibrated at 3.3 V. The device can be used from 2.16 V to 3.6 V Typical specifications are not guaranteed Digital filter cut-off frequency Time to obtain valid data after exiting Power-Down mode
LIS3LV02DL Mechanical and electrical specifications
15/48
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 3. SPI slave timing diagram (2) Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
resistors
Table 6. SPI Slave Timing Values Values are guaranteed at 8 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization
results, not tested in production
Mechanical and electrical specifications LIS3LV02DL
16/48
2.3.2 I2 C - Inter IC control interface
Subject to general operating conditions for Vdd and Top.
Figure 4. I2 C slave timing diagram (4)
4.Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
Table 7. I2C slave timing values Data based on standard I2 C protocol requirement, not tested in production A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL Cb = total capacitance of one bus line, in pF
LIS3LV02DL Mechanical and electrical specifications
17/48
2.4 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Note: Supply voltage on any pin should never exceed 6.0 V.
Table 8. Absolute maximum ratings
This is a Mechanical Shock sensitive device, improper handling can cause
permanent damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages
to the part
Mechanical and electrical specifications LIS3LV02DL
18/48
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the Earth, noting the output value, rotating
the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so, 1g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also very little over time. The Sensitivity
Tolerance describes the range of Sensitivities of a large population of sensors.
2.5.2 Zero-g level
Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal
output signal if there is no acceleration present. A sensor in a steady state on a horizontal
surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The
output is ideally in the middle of the dynamic range of the sensor (content of OUT registers
00h, 00h with 16 bit representation, data expressed as 2’s complement number). A deviation
from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress
to a precise MEMS sensor and therefore the offset can slightly change after mounting the
sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset
changes little over temperature, see “Zero-g level change vs. temperature”. The Zero-g level
of an individual sensor is stable over lifetime. The Zero-g level tolerance describes the range
of Zero-g levels of a population of sensors.
2.5.3 Self test
Self Test allows to test the mechanical and electric part of the sensor, allowing the seismic
mass to be moved by means of an electrostatic test-force. The Self Test function is off when
the self-test bit of CTRL_REG1 (control register 1) is programmed to ‘0‘. When the self-test
bit of CTRL_REG1 is programmed to ‘1‘ an actuation force is applied to the sensor,
simulating a definite input acceleration. In this case the sensor outputs will exhibit a change
in their DC levels which is related to the selected full scale and depending on the Supply
Voltage through the device sensitivity. When Self Test is activated, the device output level is
given by the algebraic sum of the signals produced by the acceleration acting on the sensor
and by the electrostatic test-force. If the output signals change within the amplitude
specified inside Table 3 or 4 then the sensor is working properly and the parameters of the
interface chip are within the defined specification.
LIS3LV02DL Functionality
19/48
3 Functionality
The LIS3LV02DL is a high performance, low-power, digital output 3-axis linear
accelerometer packaged in an LGA package. The complete device includes a sensing
element and an IC interface able to take the information from the sensing element and to
provide a signal to the external world through an I2 C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the sense capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is up to 100fF.
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by
three Σ∆ analog-to-digital converters, one for each axis, that translate the produced signal
into a digital bitstream.
The Σ∆ converters are coupled with dedicated reconstruction filters which remove the high
frequency components of the quantization noise and provide low rate and high resolution
digital words.
The charge amplifier and the Σ∆ converters are operated respectively at 61.5 kHz and
20.5 kHz.
The data rate at the output of the reconstruction depends on the user selected Decimation
Factor (DF) and spans from 40 Hz to 2560 Hz.
The acceleration data may be accessed through an I2 C/SPI interface thus making the
device particularly suitable for direct interfacing with a microcontroller.
The LIS3LV02DL features a Data-Ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in digital
system employing the device itself.
The LIS3LV02DL may also be configured to generate an inertial Wake-Up, Direction
Detection and Free-Fall interrupt signal accordingly to a programmed acceleration event
along the enabled axes.
Functionality LIS3LV02DL
20/48
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).
The trimming values are stored inside the device by a non volatile structure. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be
employed during the normal operation. This allows the user to employ the device without
further calibration.
LIS3LV02DL Application hints
21/48
4 Application hints
4.1 Soldering Information
The LGA-16 package is compliant with the ECOPACK® , RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at /mems.
Digital interfaces LIS3LV02DL
22/48
5 Digital interfaces
The registers embedded inside the LIS3LV02DL may be accessed through both the I2 C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2 C interface, CS
line must be tied high (i.e connected to Vdd_IO).
5.1 I2 C serial interface
The LIS3LV02DL I2 C is a bus slave. The I2 C is employed to write the data into the registers
whose content can also be read back.
The relevant I2 C terminology is given in the table below.
There are two signals associated with the I2 C bus: the Serial Clock Line (SCL) and the
Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the
data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS3LV02DL. When the bus is free both the lines are high.
The I2 C interface is compliant with Fast Mode (400 kHz) I2 C standards as well as the
Normal Mode.
Table 9. Serial interface pin description
Table 10. Serial interface pin description
LIS3LV02DL Digital interfaces
23/48
5.1.1 I2 C operation
The transaction on the bus is started through a ST ART (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master. The Slave ADdress (SAD) associated to the LIS3LV02DL is 0011101b.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2 C embedded inside the LIS3LV02DL behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a salve address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7
LSb represent the actual register address while the MSB enables address auto increment. If
the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented
to allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged.
Table 11. Transfer when master is writing one byte to slave
Table 12. Transfer when master is writing multiple bytes to slave
Table 13. Transfer when master is receiving (reading) one byte of data from slave
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Digital interfaces LIS3LV02DL
24/48
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. DATA is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to ‘1’ while SUB(6-0) represents the
address of first register to read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
5.2 SPI bus interface
The LIS3LV02DL SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Figure 6. Read and write protocol
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end.
SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when
CS is high (no transmission).
SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven
at the falling edge of SPC and should be captured at the rising edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
