LIS35DETR ,MEMS motion sensor 3-axisAbsolute maximum ratings . . . . 112.5 Terminology . . . . . . . 122.5.1 Sensitivity ..
LIS3DH ,MEMS digital output motion sensor ultra low-power high performance 3-axes "nano" accelerometerfeatures ultra low-power operational modes that allow advanced power saving and smart ■ 16 bit data ..
LIS3DHTR ,MEMS digital output motion sensor ultra low-power high performance 3-axes "nano" accelerometerApplicationshost processor intervention reduction. The LIS3DH is available in small thin plastic la ..
LIS3L02AL , MEMS INERTIAL SENSOR: 3-axis - /-2g ultracompact linear accelerometer
LIS3L02ALTR , MEMS INERTIAL SENSOR: 3-axis - /-2g ultracompact linear accelerometer
LIS3L02AQ ,INERTIAL SENSOR: 3AXISLIS3L02AQINERTIAL SENSOR:3Axis - 2g/6g LINEAR ACCELEROMETERPRODUCT PREVIEW■ 3V TO 5.25V SINGLE SUPP ..
LM324A ,Quad Operational AmplifierABSOLUTE MAXIMUM RATINGS Symbol Parameter LM124A LM224A LM324A UnitVSupply voltage ±16 or 32 ..
LM324A ,Quad Operational AmplifierABSOLUTE MAXIMUM RATINGS Symbol Parameter LM124A LM224A LM324A UnitVSupply voltage ±16 or 32 ..
LM324A ,Quad Operational AmplifierLM124ALM224A - LM324ALOW POWER QUAD OPERATIONAL AMPLIFIERS ■ WIDE GAIN BANDWIDTH : 1.3MHz ■ LA ..
LM324A ,Quad Operational AmplifierElectrical Characteristics for LMx24A andLM324KA.... 6 12.2 Related Links.. 156.8 Operating Conditi ..
LM324A ,Quad Operational AmplifierBlock Diagram... 102 Applications..... 18.3 Feature Description.... 113 Description....... 18.4 Dev ..
LM324-A ,Quad Operational AmplifierSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareLM224K,LM224KA,LM324 ..
LIS35DETR
MEMS motion sensor 3-axis
April 2009 Doc ID 15594 Rev 1 1/39
LIS35DEMEMS motion sensor
3-axis - ±2g/±8g smart digital output “piccolo” accelerometer
Feature 2.16 V to 3.6 V supply voltage 1.8V compatible IOs < 1 mW power consumption ±2g/±8g dynamically selectable full-scaleI2 C/SPI digital output interface Programmable multiple interrupt generator Click and double click recognition Embedded high pass filter 10000g high shock survivability ECOPACK® RoHS and “Green” compliant
(see Section8)
Applications Free-fall detection Motion activated functions Gaming and virtual reality input devices Vibration monitoring and compensation
DescriptionThe LIS35DE is an ultra compact low-power three
axis linear accelerometer. It includes a sensing
element and an IC interface able to provide the
measured acceleration to the external world
through I2 C/SPI serial interface.
The sensing element, capable of detecting the
acceleration, is manufactured using a dedicated
process developed by ST to produce inertial
sensors and actuators in silicon.
The IC interface is manufactured using a CMOS
process that allows to design a dedicated circuit
which is trimmed to better match the sensing
element characteristics.
The LIS35DE has dynamically user selectable full
scales of ±2g/±8g and it is capable of measuring
accelerations with an output data rate of 100 Hz
or 400 Hz.
The device may be configured to generate inertial
wake-up/free-fall interrupt signals when a
programmable acceleration threshold is crossed
at least in one of the three axes. Thresholds and
timing of interrupt generators are programmable
by the end user on the fly.
The LIS35DE is available in plastic Thin Land
Grid Array package (TGA) and it is designed to
operate over an extended temperature range from
-40°C to +85°C.
Table 1. Device summary
Contents LIS35DE2/39 Doc ID 15594 Rev 1
Contents Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.2 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.3 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.3 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
LIS35DE Contents
Doc ID 15594 Rev 1 3/39
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 25
7.4 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.6 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.7 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.8 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.9 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.10 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.11 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.12 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.13 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.14 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.15 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.16 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.17 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.18 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.19 CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.20 CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.21 CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.22 CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.23 CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of tables LIS35DE
4/39 Doc ID 15594 Rev 1
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Mechanical characteristics @ Vdd=2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Electrical characteristics @ Vdd=2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 18
Table 14. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18
Table 15. Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 18
Table 16. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 18. CTRL_REG1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 19. CTRL_REG2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 20. CTRL_REG2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22. CTRL_REG3 [interrupt CTRL register] (22h) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. CTRL_REG3 [interrupt CTRL register] (22h) register description . . . . . . . . . . . . . . . . . . . 26
Table 24. Data signal on Int pad control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 25. STATUS_REG (27h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 26. STATUS_REG (27h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 27. OUT_X (29h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 28. OUT_Y (2Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 29. OUT_Z (2Dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 30. FF_WU_CFG_1 (30h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 31. FF_WU_CFG_1 (30h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 32. FF_WU_SRC_1 (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 33. FF_WU_SRC_1 (31h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 34. FF_WU_THS_1 (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 35. FF_WU_THS_1 (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 36. FF_WU_DURATION_1 (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 37. FF_WU_DURATION_1 (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 38. FF_WU_CFG_2 (34h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 39. FF_WU_CFG_2 (34h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 40. FF_WU_SRC_2 (35h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 41. FF_WU_SRC_2 (35h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 42. FF_WU_THS_2 (36h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 43. FF_WU_THS_2 (36h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 44. FF_WU_DURATION_2 (37h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 45. FF_WU_DURATION_2 (37h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 46. CLICK_CFG (38h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 47. CLICK_CFG (38h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 48. Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 49. CLICK_SRC (39h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LIS35DE List of tables
Doc ID 15594 Rev 1 5/39
Table 50. CLICK_SRC (39h) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 51. CLICK_THSY_X (3Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 52. CLICK_THSY_X (3Bh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 53. CLICK_THSZ (3Ch) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 54. CLICK_THSZ (3Ch) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 55. CLICK_TimeLimit (3Dh) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 56. CLICK_Latency (3Eh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 57. CLICK_Window (3Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of figures LIS35DE
6/39 Doc ID 15594 Rev 1
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. LIS35DE electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Multiple bytes SPI Read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Multiple bytes SPI Write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. LGA14: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LIS35DE Block diagram and pin description
Doc ID 15594 Rev 1 7/39
Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Figure 2. Pin connection
Block diagram and pin description LIS35DE
8/39 Doc ID 15594 Rev 1
Table 2. Pin description
LIS35DE Mechanical and electrical specifications
Doc ID 15594 Rev 1 9/39
Mechanical and electrical specifications
2.1 Mechanical characteristics
T = 25°C unless otherwise noted
Table 3. Mechanical characteristics @ Vdd=2.5 V(1) The product is factory calibrated at 2.5 V. The device can be used from 2.16 V to 3.6 V. Typical specifications are not guaranteed. Verified by wafer level test and measurement of initial offset and sensitivity. Typical zero-g level offset value after MSL3 preconditioning. ODR is output data rate. Refer to Table 4 for specifications.
Mechanical and electrical specifications LIS35DE
10/39 Doc ID 15594 Rev 1
2.2 Electrical characteristics
T = 25°C unless otherwise noted
Table 4. Electrical characteristics @ Vdd=2.5 V (1) The product is factory calibrated at 2.5V. The device can be used from 2.16 V to 3.6 V. Typical specification are not guaranteed. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off. Filter cut-off frequency. Time to obtain valid data after exiting power-down mode.
LIS35DE Mechanical and electrical specifications
Doc ID 15594 Rev 1 11/39
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 3. SPI slave timing diagram (a) When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up
resistors
Table 5. SPI slave timing values Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port
Mechanical and electrical specifications LIS35DE
12/39 Doc ID 15594 Rev 1
2.3.2 I2 C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
Figure 4. I2 C Slave timing diagram (b)
Table 6. I2 C slave timing values Data based on standard I2 C protocol requirement, not tested in production Cb = total capacitance of one bus line, in pF Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port
LIS35DE Mechanical and electrical specifications
Doc ID 15594 Rev 1 13/39
2.4 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Note: Supply voltage on any pin should never exceed 6.0 V
Table 7. Absolute maximum ratings
This is a mechanical shock sensitive device, improper handling can cause permanent
damages to the part
This is an ESD sensitive device, improper handling can cause permanent damages to
the part
Mechanical and electrical specifications LIS35DE
14/39 Doc ID 15594 Rev 1
2.5 Terminology
2.5.1 Sensitivity
Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g
acceleration to it. As the sensor can measure DC accelerations this can be done easily by
pointing the axis of interest towards the center of the Earth, noting the output value, rotating
the sensor by 180 degrees (point to the sky) and noting the output value again. By doing so,1g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor. This
value changes very little over temperature and also very little over time. The Sensitivity
Tolerance describes the range of Sensitivities of a large population of sensor.
2.5.2 Zero-g level
Zero-g level Offset (Off) describes the deviation of an actual output signal from the ideal
output signal if there is no acceleration present. A sensor in a steady state on a horizontal
surface will measure 0g in X axis and 0g in Y axis whereas the Z axis will measure 1g. The
output is ideally in the middle of the dynamic range of the sensor (content of OUT registers
00h, data expressed as 2’s complement number). A deviation from ideal value in this case is
called Zero-g offset. Offset is to some extent a result of stress to a precise MEMS sensor
and therefore the offset can slightly change after mounting the sensor onto a printed circuit
board or exposing it to extensive mechanical stress. Offset changes little over temperature,
see “Zero-g level change vs. temperature”. The Zero-g level of an individual sensor is stable
over lifetime. The Zero-g level tolerance describes the range of Zero-g levels of a population
of sensors.
2.5.3 Click and double click recognition
The click and double click recognition functions help to create man-machine interface with
little software overload. The device can be configured to output an interrupt signal on
dedicated pin when tapped in any direction.
If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial
interrupt pin (INT1 and/or INT2). A more advanced feature allows to generate and interrupt
request when a “double click” with programmable time between the two events enabling a
“mouse button like” use.
This function can be fully programmed by the user in terms of expected amplitude and
timing of the stimuli.
LIS35DE Functionality
Doc ID 15594 Rev 1 15/39
3 Functionality
The LIS35DE is a ultracompact, low-power, digital output 3-axis linear accelerometer
packaged in a LGA package. The complete device includes a sensing element and an IC
interface able to take the information from the sensing element and to provide a signal to the
external world through an I2 C/SPI serial interface.
3.1 Sensing element
A proprietary process is used to create a surface micro-machined accelerometer. The
technology allows to carry out suspended silicon structures which are attached to the
substrate in a few points called anchors and are free to move in the direction of the sensed
acceleration. To be compatible with the traditional packaging techniques a cap is placed on
top of the sensing element to avoid blocking the moving parts during the moulding phase of
the plastic encapsulation.
When an acceleration is applied to the sensor the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the sense capacitor.
At steady state the nominal value of the capacitors are few pF and when an acceleration is
applied the maximum variation of the capacitive load is in fF range.
3.2 IC interface
The complete measurement chain is composed by a low-noise capacitive amplifier which
converts into an analog voltage the capacitive unbalancing of the MEMS sensor and by
analog-to-digital converters.
The acceleration data may be accessed through an I2 C/SPI interface thus making the
device particularly suitable for direct interfacing with a microcontroller.
The LIS35DE features a Data-Ready signal (RDY) which indicates when a new set of
measured acceleration data is available thus simplifying data synchronization in the digital
system that uses the device.
The LIS35DE may also be configured to generate an inertial Wake-Up and Free-Fall
interrupt signal accordingly to a programmed acceleration event along the enabled axes.
Both Free-Fall and Wake-Up can be available simultaneously on two different pins.
3.3 Factory calibration
The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off).
The trimming values are stored inside the device by a non volatile memory. Any time the
device is turned on, the trimming parameters are downloaded into the registers to be used
during the normal operation. This allows the user to use the device without further
calibration.
Application hints LIS35DE
16/39 Doc ID 15594 Rev 1
4 Application hints
Figure 5. LIS35DE electrical connection
The device core is supplied through Vdd line while the I/O pads are supplied through
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be
placed as near as possible to the pin 6 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO
without blocking the communication busses, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2 C/SPI interface.When using the I2 C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be
completely programmed by the user though the I2 C/SPI interface.
4.1 Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is
qualified for soldering heat resistance according to JEDEC J-STD-020C.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendation are available at .
LIS35DE Digital interfaces
Doc ID 15594 Rev 1 17/39
5 Digital interfaces
The registers embedded inside the LIS35DE may be accessed through both the I2 C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2 C interface, CS
line must be tied high (i.e connected to Vdd_IO).
5.1 I2 C serial interface
The LIS35DE I2 C is a bus slave. The I2 C is employed to write the data into the registers
whose content can also be read back.
The relevant I2 C terminology is given in the table below.
There are two signals associated with the I2 C bus: the Serial Clock Line (SCL) and the
Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the
data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor
embedded inside the LIS35DE. When the bus is free both the lines are high.
The I2 C interface is compliant with fast mode (400 kHz) I2 C standards as well as the normal
mode.
Table 8. Serial interface pin description
Table 9. Serial interface pin description
Digital interfaces LIS35DE
18/39 Doc ID 15594 Rev 1
5.1.1 I2 C operation
The transaction on the bus is started through a ST ART (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS35DE is 001110xb. SDO pad can be used to
modify less significant bit of the device address. If SDO pad is connected to voltage supply
LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’
(address 0011100b). This solution permits to connect and address two different
accelerometer to the same I2 C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data has
been received.
The I2 C embedded inside the LIS35DE behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a salve address is sent, once a
slave acknowledge (SAK) has been returned, a 8-bit sub-address is transmitted: the 7 LSb
represent the actual register address while the MSB enables address auto increment. If the
MSb of the SUB field is 1, the SUB (register address) is automatically incremented to allow
multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the Master will transmits to the slave with direction unchanged. Table 10 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 10. SAD+Read/Write patterns
Table 11. Transfer when Master is writing one byte to slave
LIS35DE Digital interfaces
Doc ID 15594 Rev 1 19/39
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to read.
In the presented communication format MAK is Master Acknowledge and NMAK is No
Master Acknowledge.
5.2 SPI bus interface
The LIS35DE SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Table 12. Transfer when Master is writing multiple bytes to slave
Table 13. Transfer when Master is receiving (reading) one byte of data from slave
Table 14. Transfer when Master is receiving (reading) multiple bytes of data from
slave
Table 15. Transfer when Master is receiving (reading) multiple bytes of data from
slave
Digital interfaces LIS35DE
20/39 Doc ID 15594 Rev 1
Figure 6. Read and write protocol
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the Serial Port Clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses or
in multiple of 8 in case of multiple byte read/write. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drives SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remains unchanged in multiple read/write
commands. When 1, the address is auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is 0 the address used to read/write data remains the same for every block. When MS bit
is 1 the address used to read/write data is incremented at every block.
The function and the behavior of SDI and SDO remain unchanged.
