LH4006D ,+/-8 V, +/-100 mA, precision RF closed loop bufferApplications
I Line drivers
I Video buffers
I Pulse amplifiers
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LH4006D
+/-8 V, +/-100 mA, precision RF closed loop buffer
LH4006/LH40066
National
I Semiconductor
PRELIMINARY
LH4006/LH4006C Precision RF Closed Loop Buffer
General Description
The LH4006 is a precision RF buffer optimized for unity gain
applications. It features a small signal bandwidth of 350
MHz. The buffer is internally compensated to be unity gain
stable and has internal short circuit protectlon. The LH4006
is useful in applications such as video buffering, cable driv-
ing, and flash converter input conditioning. The high band-
width also allows the LH4006 to be used in RFIIF signal
conditioning such as amplification or down converslon.
Features
I: Operation from 16V supplies
" Drives son directly
I: Internal power supply bypassing
a Short circuit protection
I: 1000 les slew rate
a 0.95 gain accuracy Into 500
Applications
I: Line drivers
I: Video buffers
a Pulse amplifiers
Connection Diagram
{DONGU‘O‘N‘
tle 12
I’EEDBACK
OUTPUT
TL/K19255-1
Top Vlew
Note 1: NC = not connecked.
Note 2: Pins 9 a 17 are internally connected.
Order Number LH4006D t LH40060D
See NS Package Number DMD
Absolute Maximum Ratings
If Mllllary/Aerospace speclfled devlces are required,
please contact the Natlonal Semlconductor Sales
Operating Temperature Range, TA
LH4006CD
Office/Dlstrlbutors for availability and spttttotatlorta.
LH4006D
- 25'C to + 85°C
-55'C to + 125''C
OQOOVH'l/9007H1
Supply Voltage, Vs k 8V Storage Temperature Range, TSTG - 65''C to + 150%
Power Dissipation, PD Maximum Junction Temperature, TJ 150°C
To = 25:0, Derate .L.inear.ly at 33.3:C/W 3.75W Lead Temperature (Soldering < 10 sec.) 300°C
TA - 25 C, Derate Lunearly at 62.5 C/W 2W ESD Rating to be determi n e d.
Input Common Mode Voltage Range, VCM t vs
Output Current, lo , 100 mA
Output Short Circuit Duration Continuous
DC Electrical Characteristics (Notes1&6)
Vs = 16V, Rs = RL = 500, TA = 25°C unless otherwise noted.
LH4006tt Urtlttt
Symbol Parameter Conditions Tested Llmlt Design lelt (Max unless
Typ (Note 2) (Note 3) otherwlse stated)
Vos OutputOffsetVoltage TA = Tu = 25'C, Note4 5 15 mV
VOS/AT Offset Voltage Drift 100 p.V/°C
la Input Bias Current Rs = Mon, Note 4 100 300 pLA
AV Voltage Gain Ve: = 2Vp-p, RL = 500 0.98 0.95 NIN
f: 1 kHz RL = 1m 0.98 0.95 (min)
Vo Output Voltage Swing AV = +1 k 3 V
PSRR Power Supply Vs = t4Vto iav 55 45 dB
Rejection Ratio RL = 1 kn. (min)
ls Supply Current ViN = ov, FIL = 1 kn. 55 65 mA
Pr; Power Dissipation Note 7 780 mW
AC Electrical Characteristics (Note1)
VS = i6V, Rs == RL = 509. TA = 25'C unless otherwise noted.
Symbol Parameter Conditions Tested Limit Design Limit (Max unless
Typ (Note 2) (Note 3) otherwise stated)
tr Small Signal Rise Time AVIN = 0.5V 2 ns
ts Settling Time to 0.1 % VIN = i av 80
SR Slew Rate VIN = -3Vto +3v 10%-90% 1000 vms
VIN = +3Vt0 -3V 10%-90% 1200 (min)
f-a dB Small Signal VOUT = 100 mVp-p Av = +1 350 300
Bandwidth MHz
. (min)
Full Power Bandwidth " = i2V. Note 5 80
Second Order Voor = 4 Vp-p, - 60 dB
Harmonic Distortion m = 10 MHz
LH4006/LH4OOGC
DC Electrical Characteristics (Notes1 &6)
Vs = -+6V, Rs = Rt. = 500. TA = 25% unless otherwise noted.
LH4008 Unlts
Symbol Parameter Condluons Tested Umlt Dealgn lelt (Max unless
Typ (Note 2) (Note 3) otherwlae stated)
Vos Output Offset Voltage TA = T J = 25''C 2 15 mV
VOS/AT OffststVoltage Drift VIN = ov 100 pV/''C
lg Input Bias Current Rs = Mon 100 300 A
TA = Tg = 25''C, Note4 40° "
AV Voltage Gain VIN = 2Vp-p, RL == 50tt 0.98 0.95
f == 1 kHz 0.93 V/V
RL = 1m 0.98 0.95 (min)
V0 OutpulVoltage AV = +1 i3 13 V
Swing (min)
PSRR PowerSupply Vs = 14Vto +8V 55 45 dB
Rejection Ratio ao (min)
ls Supply Current " = 0V, RL = 1 kn 55 65 so mA
PD Power Dissipation (Note 7) 780 mW
AC Electrical Characteristics (Note1)
Vs = i6V, Rs = RL = 500, TA = 25'C unless otherwise noted.
LH4006 Units
Symbol Parameter Conditlons Tested lelt Deslgn lelt (Max unless
Typ (Note 2) (Note 3) otherwise stated)
tr Small Signal Rise Time AVIN = 0.5V 2 ns
ts Settling Time to 0.1% VIN = i av 80
SR Slew Rate VIN = -3V to +3V 10%-90% 1000 Wps
" = +3Vto -3V 10%-90% 1200 (min)
f-s dB Small Signal VOUT = 100 mVp-p AV = +1 350 300
Bandwidth MHz
Full Power Bandwidth " = i2V. Note 5 80
Second Order VOUT = 4 Vp-p, _ 60 dB
Harmonic Distortion fm = 10 MHz
Note 1: These measurements are taken with the LH4006 strapped for a gain of + I.
Note 2: Tested limits are guaranteed and 100% testtad in production.
Not. 3: Design limits are guaranteed (but not 100% production tested) over indicated tampera1ure and supply voltage ranges. These limits are not used to
calculate outgoing quality levels.
Note 4: Specification is at 25t junction temperature due to requirements of high speed automatic testing. Actual value may be higher at operating junction
temperature.
Note 5: Full power bandwidth is calculated based on slew rate measurement using FPBW = slaw rate/(2 rv peak).
Noie s: Boldiaco limits are guaranteed over lull temperature. Operating ambient temperature range of LHAOOBC is - 25'0 to + 85°C, and LH4006 is - 55'0 to
+ 125'C.
Note T: When the LH4006 is operated at elevated terrpsrature (such as 125°C), some term of heat sinking or forced air cooling is required. The quiescent powev
with Vs of k 6V is 780 mW, whereas the package is rated to 750 mW without a heatsink at 125°C.
Typical Performance Characteristics
Maximum Power
Dissipation
" Time
" A 175
A 4.0 CASE
z M 'roc=ss.3oe w E 150
g M it 125
g M 8 100
L5 M g 75
= IS AMBIENT ti 50
2 " 'U=usoc/ _ _ g
o 25 so 75 too 125 150 0.1
mpmmkwc)
TL/K/9255-2
Application Information
The unity gain follower configuration shown in Figure 1, of-
fers a 350 MHz small signal bandwidth to the --3 dB point
and the minimum slew rate of 1000 V/ps insures a full pow-
er bandwidth of 80 MHz for tt 4V peak to peak signal, ac-
cording to the formula:
Input Blas Current
ms (UM)
Offset Voltage (Typical)
vs Time
orrsn vomc: (mV)
10 0.1 1 10
m1: (mu)
TL/K/9255-10 TL/K/9255-11
Where SR is the slew rate in V/ps, B is the bandwidth of the
device in MHz for a peak sine wave voltage Vp.
The unity gain follower/buffer is therefore an excellent
choice for wideband sinewave buffering or pulse amplifica-
tion. Figure 2 shows the typical pulse response for such a
configuration.
TOP = Input
BOTTOM = Output
TL/kf9255-3
FIGURE 1. Unity Gain Follower
TL/KI9255-5
v06 = A6V,Rs = Rt. = 50n.
FIGURE 2. Follower/Butter Pulse Response
OQDOVH'l/QDOPH'I
LH4006/LH4006C
Driving Capacitive Loads
Flash AID, unterminated cables, etc. can exhibit up to 300
pF of capacitance, thus creating stability or settling prob-
lems. Figure 3 shows the compensation scheme for driving
such capacitive loads while still insuring optimum settling.
The output current limit of the LH4006 is a considerable
help for driving capacitive loads, the charging current is kept
in control and the damping resistor can be small without
overloading the output stage. A 20tt resistor in series with
the capacitance is required for insuring an optimum settling
time to 0.5% in less than 20 ns which is suitable for driving a
7 bit flash A to D converter in video applications at a sam-
pling rate of 20 MSPS (see Figure 4).
TL/K/9255-6
FIGURE 3. Driving Capacitance
faaaa=ssz=za== TOP = Input
(Wm: MTTOM == Output
asCTFr======raa
a2===ir9
====l=?
"i/dw g
JRisslb
TVK/9255--7
Vcc = 26 Volts
tk. - 360 pF
FIGURE 4. Pulse Response When Drlvlng Capacitance
Layout Considerations
The layout of a RFlVideo PC board where the signal fre-
quency is beyond 100 MHz requires special attention. All
the traces or connections must be as short and as wide as
possible in order to keep their parasitic inductance to a mini-
mum. This is especially critical for the supply lines where the
current can reach over 100 mA in a few nanoseconds.
Although the LH4006 contains internal decoupling, it still
requires some external bypassing capacitors. which have to
be located as close to the supply pins as possible. A 4.7 p.F
in parallel with a 100 nF low inductance capacitor will insure
good filtering. in some cases of noisy environment, or when
the power supply is located far from the circuit, it may be
necessary to use a dual stage decoupling as shown in Fig-
ure 5.
TLfK/9255-8
FIGURE ti. Dual Stage Decoupling
Ground can also become a considerable problem. It is as-
sumed to be uniformly zero volts and considered as a refer-
ence. In practice, if the ground is poorly laid out, every sin-
gle point may be at a different potential and at a different
phase, which is a source of instability or signal distortion.
The most reliable solution to this problem is to have a
ground plane that will minimize the parasitic inductance and
therefore, potential and phase differences.
Input Capacitance
The input capacitance of the LH4006 is typically 8 pF and
will slightly increase with frequency. A large source resist-
ance value in front of this will form a pole, which may sub.
stantially reduce the bandwidth of the circuit and affect sta-
bility.
This is the reason why resistor values higher than soon
should not be used in the feedback network and high
source impedance should be avoided.
Bias Current
The input bias current is typically 100 pA and may create an
undesirable output offset voltage when the source imped-
ance is high. An internal son resistor is provided for match-
ing with a son source impedance in order to minimize the
output offset voltage. Figure 6 shows a circuit that uses a
FET transistor pair for the input Mags in order to reduce the
input bias current to the sub-nanoampere region.
1/2 2N591l
TL/ Kl9255 -9
FIGURE 6. FET Input Follower Butter
OSOOVH'I/QOOVH'I
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
LH4006CD - product/lh4006cd?HQS=T|-nu|I-null-dscataIog-df-pf-null-wwe
LH4006D - product/Ih4006d?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nuII-wwe
