L9942 ,Stepper Motor Driver for Bipolar Motors with microstepping & programmable current profileFunctional description of the logic with SPI . . . . . 214.1 Motor stepping clock input (STEP) ..
L9942XP1 ,Stepper Motor Driver for Bipolar Motors with microstepping & programmable current profileelectrical characteristics . . . . . . . 286.1 Inputs: CSN, CLK, STEP, EN and DI . . . . 286. ..
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L9947L ,QUAD HALF-BRIDGE AND SINGLE HIGH-SIDE DRIVERELECTRICAL CHARACTERISTICS ° (VS = 8 to 16V; VCC = 4.5 to 5.5V; Tj = -40 to 150 C;unless other-wise ..
L9947S ,QUAD HALF-BRIDGE AND SINGLE HIGH-SIDE DRIVERfunctional description (pag....)|I | Output Current Limitation to 0.67 2 AOUT2 Supply or GND|I | Ou ..
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L9942-L9942XP1-L9942XP1TR
Stepper Motor Driver for Bipolar Motors with microstepping & programmable current profile
September 2013 Doc ID 11778 Rev 7 1/40
L9942Integrated stepper motor driver for bipolar stepper motors
with microstepping and programmable current profile
Features Two full bridges for max. 1.3 A load DSON = 500 m) Programmable current waveform with look-up
table: 9 entries with 5 bit resolution Current regulation by integrated PWM
controller and internal current sensing Programmable stepping mode: full, half, mini
and microstepping Programmable slew rate for EMC and power
dissipation optimization Programmable Fast-, Slow-, Mixed- and Auto-
Decay Mode Full-scale current programmable with 3 bit
resolution Programmable stall detection Step clock input for reduced µController
requirements Very low current consumption in standby mode
IS < 3 µA, typ. Tj 85 °C All outputs short circuit protected with
openload, overload current, temperature
warning and thermal shutdown The PWM signal of the internal PWM controller
is available as digital output. All parameters are guaranteed for 3 V < Vcc <
5.3 V and for 7 V < Vs < 20 V
ApplicationsStepper motor driver for bipolar stepper motors in
automotive applications like light levelling,
Bending light and Throttle control.
DescriptionThe L9942 is an integrated stepper motor driver
for bipolar stepper motors with microstepping and
programmable current profile look-up-table to
allow a flexible adaptation of the stepper motor
characteristics and intended operating conditions.
It is possible to use different current profiles
depending on target criteria: audible noise,
vibrations, rotation speed or torque. The decay
mode used in PWM-current control circuit can be
programmed to slow-, fast-, mixed-and auto-
decay. In autodecay mode device will use slow
decay mode if the current for the next step will
increase and the fast decay or mixed decay mode
if the current will decrease. The programmable
stall detection is useful in case of head lamp
leveling and bending light application, by
preventing to run the motor too long time in stall
for position alignment. If a stall is detected, the
alignment process is closed and the noise is
minimized.
Table 1. Device summary
Contents L99422/40 Doc ID 11778 Rev 7
Contents Block diagram and pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Dual power supply: VS and V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 T emperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 PWM current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.3 Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.4 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.5 Outputs: Qxn (x = A; B n = 1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.6 PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional description of the logic with SPI . . . . . . . . . . . . . . . . . . . . . 214.1 Motor stepping clock input (STEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 PWM output (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L9942 ContentsDoc ID 11778 Rev 7 3/40
4.4 Chip select not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Serial data in (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Serial data out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8 Data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI - control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235.1 Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3 Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6 Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7 Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8 Auxiliary logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.1 Fault condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.2 SPI communication monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.3 PWM monitoring for stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Logic with SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 286.1 Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4 Output: DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.6 STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337.1 Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Step clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Load current control and detection of overcurrent (shortages at outputs) 33
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
List of tables L9942
4/40 Doc ID 11778 Rev 7
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Over- and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Reference current output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Charge pump output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Outputs: Qxn (x = A; B n =1; 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. PWM control (see Figure 4 and Figure 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. Register 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. Inputs: CSN, CLK, STEP, EN and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. DI timing (see Figure 11 and Figure 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 23. Outputs: DO, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 24. Output: DO timing (see Figure 12 and Figure 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 25. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 26. STEP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
L9942 List of figures
Doc ID 11778 Rev 7 5/40
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Stepping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Thermal data of the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. VS monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Logic to set load current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Switching on minimum time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. SPI and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12. SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13. DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Timing of status bit 0 (fault condition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Stall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. Reference generation for PWM control (switch on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Reference generation for PWM control (decay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. PowerSSO24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 38
Block diagram and pin information L9942 Block diagram and pin information
Figure 1. Block diagram
Figure 2. Pin connection (top view)
L9942 Block diagram and pin information
Doc ID 11778 Rev 7 7/40
Table 2. Pin description
Block diagram and pin information L9942
8/40 Doc ID 11778 Rev 7
Table 2. Pin description (continued)
L9942 Device description
Doc ID 11778 Rev 7 9/40
2 Device description
2.1 Dual power supply: VS and V CC
The power supply voltage VS supplies the half bridges. An internal charge-pump is used to
drive the highside switches. The logic supply voltage VCC (stabilized) is used for the logic
part and the SPI of the device. Due to the independent logic supply voltage the control and
status information will not be lost, if there are temporary spikes or glitches on the power
supply voltage. In case of power-on (VCC increases from undervoltage to VPOR OFF = 2.60V,
typical) the circuit is initialized by an internally generated power-on-reset (POR). If the
voltage VCC decreases under the minimum threshold (VPOR ON = 2.3 V, typical), the outputs
are switched to tristate (high impedance) and the internal registers are cleared.
2.2 Standby mode
The EN input has a pull-down resistor. The device is in standby mode if EN input isn't set to
a logic high level. All latched data will be cleared and the inputs and outputs are switched to
high impedance. In the standby mode the current at VS (VCC) is less than 3 µA (1 µA) for
CSN = high (DO in tristate). If EN is set to a logic high level then the device will enter the
active mode. In the active mode the charge pump and the supervisor functions are
activated.
2.3 Diagnostic functions
All diagnostic functions (overload/-current, open load, power supply over-/undervoltage,
temperature warning and thermal shutdown) are internally filtered (tGL = 32 µs, typical) and
the condition has to be valid for a minimum time before the corresponding status bit in the
status registers will be set. The filters are used to improve the noise immunity of the device.
Open load and temperature warning function are intended for information purpose and will
not change the state of the bridge drivers. On contrary, the overload/-current and thermal
shutdown condition will disable the corresponding driver (overload/-current) or all drivers
(thermal shutdown), respectively. The microcontroller has to clear the status bit to reactivate
the bridge driver.
2.4 Overvoltage and undervoltage detection
If the power supply voltage Vs rises above the overvoltage threshold VSOV OFF (typical V), an overvoltage condition is detected. Programmable by SPI (OVW) the outputs are
switched to high impedance state (default after reset) or the overvoltage bit is set without
switching the outputs to high impedance. When the voltage Vs drops below the under-
voltage threshold VSUV OFF, the outputs are switched to high impedance state to avoid the
operation of the power devices without sufficient gate driving voltage (increased power
dissipation). Error condition is latched and the microcontroller needs to clear the status bits
to reactivate the drivers.
Device description L9942
10/40 Doc ID 11778 Rev 7
2.5 Temperature warning and thermal shutdown
If junction temperature rises above Tj TW a temperature warning flag is set which is
detectable via the SPI. If junction temperature increases above the second threshold Tj SD,
the thermal shutdown bit will be set and power DMOS transistors of all output stages are
switched off to protect the device. In order to reactivate the output stages the junction
temperature must decrease below Tj SD -Tj SD HYS and the thermal shutdown bit has to be
cleared by the microcontroller.
2.6 Inductive loads
Each half bridge is built by an internally connected highside and a low-side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven without external free-wheeling diodes. In order to reduce the power dissipation during
free-wheeling condition the PWM controller will switch-on the output transistor parallel to the
freewheeling diode (synchronous rectification).
2.7 Cross-current protection
The four half-brides of the device are cross-current protected by an internal delay time
depending on the programmed slew rate. If one driver (LS or HS) is turned-off then
activation of the other driver of the same half bridge will be automatically delayed by the
cross-current protection time.
2.8 PWM current regulation
An internal current monitor output of each high-side and low-side transistor sources a
current image which has a fixed ratio of the instantaneous load current. This current images
are compared with the current limit in PWM control. Range of limit can reach from
programmed full scale value (register1 DAC Scale) down belonging LSB value of 5 bit DAC
(register1 DAC Phase x). The data of the two 5 bit DACs comes form set up in 9 current
profiles (register2 to 6). If signal changes to logic high at pin STEP then 2 current profiles
are moved in register1 for DAC Phase A and B. Number of profile depends on phase
counter reading and direction bit in register0 (Figure 7). The bridges are switched on until
the load current sensed at HS switch exceeds the limit. Load current comparator signal is
used to detect open load or overcurrent condition also.
2.9 Decay modes
During off-time the device will use one of several decay modes programmable by SPI
(Figure 4 top). In slow decay mode HS switches are activated after cross current protection
time for synchronous rectification to reduce the power dissipation (Figure 4 detail A). In fast
decay opposite half bridge will switched on after cross current protection time, that is same
like change in the direction. For mixed decay the duration of fast decay period before slow
decay can be set to a fixed time (Figure 4 detail B continuous line) or is triggered by under-
run of the load current limit (Figure 4 detail B dashed line), that can be detected at LS
switch. The special mode where the actual phase counter value is taken into account to
select the decay mode is called auto decay (e.g. in Figure 3 Micro Stepping DIR=1). If the
absolute value of the current limit is higher as during step before then PWM control uses
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slow decay mode always. Otherwise one of the fast decay modes is automatic selected for a
quick decrease of the load current and so it obtains new lower target value.
2.10 Overcurrent detection
The overcurrent detection circuit monitors the load current in each activated output stage. In
HS stage it is in function after detection of current limit during PWM cycle and in LS stage it
works permanently. If the load current exceeds the overcurrent detection threshold for at
least tISC = 4 µs, the overcurrent flag is set and the corresponding driver is switched off to
reduce the power dissipation and to protect the integrated circuit. Error condition is latched
and the microcontroller needs to clear the status bits to reactivate the drivers.
2.11 Open load detection
The open load detection monitors the activity time of the PWM controller and is available for
each phase. If the limit of load current is below around 100mA then open load condition is
detectable. Open load bit for a bridge is set in the register6 if this low current limit can't
reached after at least 15 consecutive PWM cycles.
ruth table shows possible profiles for active open load detection. Maximum threshold IOL is
shown in left column if x bits are 1 (see also Figure 7). Lowest possible limit is e.g. 3.1 mA
for DC2=DC1=DC0=0 and it is set only I0=1.
2.12 Stepping modes
One full revolution can consist of four full steps, eight half steps, sixteen mini steps or 32
microsteps.
Mode is set up in register 0 and it defines increment size of phase counter. Phase counter
value defines address of corresponding current profile. Stepping modes with typical profile
values can see in Figure 3 (e.g. also so called 'T wo Phase On' shown in dashed line).
Table 3. Truth table
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Figure 3. Stepping modes
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2.13 Decay modes
Figure 4. Decay modes
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3 Electrical specifications
3.1 Absolute maximum ratings
Warning: Leaving the limitation of any of these values may cause an
irreversible damage of the integrated circuit!
3.2 ESD protection
Table 4. Absolute maximum ratings
Table 5. ESD protection HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A HBM with all unzapped pins grounded
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3.3 Thermal data
Figure 5. Thermal data of the package
Table 6. Operating junction temperature
Table 7. Temperature warning and thermal shutdown
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3.4 Electrical characteristics
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, IREF = -200 µA, unless otherwise
specified. The voltages are referred to GND and currents are assumed positive, when the
current flows into the pin.
3.4.1 Supply
Table 8. Supply This parameter is guaranteed by design.
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3.4.2 Over- and undervoltage detection
Figure 6. VS monitoring
3.4.3 Reference current output
The device works properly without the external resistor at pin REF . In this case it doesn't
have to fulfill all specified parameters.
Table 9. Over- and undervoltage detection
Table 10. Reference current output
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3.4.4 Charge pump output
The ripple of voltage at CP can suppressed using a capacity of e.g.100 nF.
3.4.5 Outputs: Qxn (x = A; B n = 1; 2)
The comparator, which is monitoring current image of HS, is working during ON cycle of
PWM control. If load current is higher as set value then the signal ILIMIT is generated and
after filter time the bridge is switched off. Test mode gets access to signal ILIMIT and
threshold of current can be measured.
Table 11. Charge pump output
Table 12. Outputs: Qxn (x = A; B n =1; 2) MIN= 0.92 · IQxnLIM – 0.02 · |IQxnFS_HS |; MAX= 1.08 · IQxnLIM + 0.02 · |IQxnFS_HS |
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Note: Current profile has to pre set with I4 I3 I2 I1 I0 = 11111 and load to register 1.
Output current limit IQxnLIM is product of full scale current |IQxnFS_ | (bits DC2 DC1 DC0) and
value of DAC Phase A/B (bits I4 I3 I2 I1 I0) in register1.
Values of DAC Phase A and B can read out and depends on set up done before: direction DIR, stepping mode ST1 ST0 and phase counter P4 P3 P2 P1 P0 in register 0 and
2. value of corresponding current profile (for address of current profile entry see also
Figure 3).
Figure 7. Logic to set load current limit
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3.4.6 PWM control
Figure 8. Switching on minimum time
Table 13. PWM control (see Figure 4 and Figure7) This parameter is guaranteed by design.
Time base is an internal trimmed oscillator of typical 2MHz and it has an accuracy of ±6 %.
