L9380-TR ,TRIPLE HIGH-SIDE MOSFET DRIVERfeatures a current source toassure defined high status when the pin is open.9 EN Enable logic signa ..
L93PI ,QUAD LOW SIDE DRIVERABSOLUTE MAXIMUM RATINGS (no damage or latch)Symbol Parameter Value UnitV Supply voltage -24 to 45 ..
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LC73861 ,DTMF Receiver LSIElectrical Characteristics at Ta = 25°C ± 2°C, V =5V,V =0V,f = 4.194304 MHzDD SS OSCParameter Symbo ..
LC73872 ,DTMF ReceiverFeatures u d. Detects all 16 DTMF signals. -"i1"1-'un I-; T. Includes on-chip all filters required ..
LC73872 ,DTMF ReceiverFeatures u d. Detects all 16 DTMF signals. -"i1"1-'un I-; T. Includes on-chip all filters required ..
LC73872 ,DTMF ReceiverOrdering number : EN4998CMOS ICLC73872MDTMF ReceiverOverview Package DimensionsThe LC73872M is a DT ..
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LC7387M ,
DTMF ReceiverElectrical Characteristics at Ta = 25°C, VDD = 5 V, vss = 0 V, fosc = 4.194304 MHz, _ Ratings _Para ..
L9380-TR
TRIPLE HIGH-SIDE MOSFET DRIVER
1/13
L9380May 2003 OVERVOLTAGE CHARGE PUMP SHUT OFF FOR VVS > 25V REVERSE BATTERY PROTECTION
(REFERRING TO THE APPLICATION
CIRCUIT DIAGRAM) PROGRAMMABLE OVERLOAD
PROTECTION FUNCTION FOR CHANNEL 1
AND 2 OPEN GROUND PROTECTION FUNCTION
FOR CHANNEL 1 AND 2 CONSTANT GATE CHARGE/DISCHARGE
CURRENT
DESCRIPTIONThe L9380 device is a controller for three external
N-channel power MOS transistors in "High-Side
Switch" configuration. It is intended for relays re-
placement in automotive electric control units.
TRIPLE HIGH-SIDE MOSFET DRIVER
PIN CONNECTION (Top view)
L9380 2/13
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGSNote: ESD for all pins, except the timer pins, are according to MIL 883C, tested at 2KV, corresponds to a maximum energy dissipation of 0.2mJ.
The timer pins are tested with 800V
3/13
L9380
THERMAL DATA
LIFE TIME
PIN DESCRIPTION
L9380 4/13
ELECTRICAL CHARACTERISTCS (7V ≤ VS ≤ 18.5V; -40°C ≤ TJ ≤ 150°C, unless otherwise specified.)NOTE: Not measured guaranteed by design
Function is given for supply voltage down to 5.5V. Function means: The channels are controlled from the
inputs, some other parameters may exceed the limit. In this case the programming voltage and timer
threshold will be lower. This leads to a lower protection threshold and time.
5/13
L9380
Figure 1. Timing Characteristic.
FUNCTIONAL DESCRIPTIONThe Triple High-Side Power-MOS Driver features all necessary control and protection functions to switch
on three Power-MOS transistors operating as High-Side switches in automotive electronic control units.
The key application field is relays replacement in systems where high current loads, usually motors with
nominal currents of about 40A connected to ground, has to be switched.
A high signal at the EN pin enables all three channels. With enable low gates are clamped to ground. In
this condition the gate sink current is higher than the specified 3mA. An enable low signal makes also a
reset of the timer.
A low signal at the inputs switch on the gates of the external MOS. A short circuit at the input leads to
permanent activation of the concerned channel. In this case the device can be disabled with the enable
pin. The charge pump loading is not influenced due to the enable input.
An external N-channel MOS driver in high side configuration needs a gate driving voltage higher than VS.
It is generated by means of a charge pump with integrated charge transfer capacitors and one external
charge storage capacitor CCP.
The charge pump is dimensioned to load a capacitor CCP of 33nF in less than 20ms up to 8V above VS.
The value of CCP depends on the input capacitance of the external MOS and the decay of the charge
pump voltage down to that value where no significant influence on the application occurs.
The necessary charging time for CCP has to be respected in the sequence of the input control signals.
As a consequence the lower gate to source voltage can cause a higher drop across the Power-MOS and
get into overload condition. In this case the overload protection timer will start.
After the protection time the concerned channel will be switched off. Channel 3 is not equipped with an
overload protection. The same situation can occur due to a discharge of the storage capacitor caused by
the gate short to ground. The gate driver that is supplied from the pin CP, which is the charge pump output,
has a sink and source current capability of 3mA. For a short-circuit of the load (source to ground) the
L9380 has no gate to source limitation. The gate source protection must be done externally.
L9380 6/13
Figure 2. Drain, source input current.Channel 1 and 2 provide drain to source voltage sensing possibility with programmable shut-off delay
when the activation threshold was exceeded.
This threshold VDSmin is set by the external resistor RD. The bias current flowing through this resistor is
determined by the programming resistor RPR. This external resistor RPR defines also the charge and dis-
charge current of the timer capacitor CCT. The drain to source threshold VDSmin and the timer shut off delay
time Toff can be calculated:
VDSmin = VPR (RD /RPR)
Toff = 4.4 CT RPR
In application which don’t use the overload protection or if one channel is not used, the Timer pin of this
channel must be connected to ground and the drain pin with a resistor to Vbat.
The timing characteristic illustrates the function and the meaning of VDSmin and Toff (see figure 4). The
input current of the overload sense comparator is specified as ISmax. The sum IPR + IDmax generates a drop
across the external resistor RD if the drain pin voltage is higher than the source pin (see Fig. 2). In the
switching point the comparator input source pin currents are equal and the half of the specified current
ISmax. For an offset compensation equal external resistors (RD = RS) at drain and source pin are impera-
tive. The drain sense comparator, which detects the overload, has a symmetrical hysteresis of 20mV (see
Fig. 3).
Exceeding the source pin voltage by 10mV with respect to the drain voltage forces the timer capacitor to
discharge. Decreasing the source pin voltage 10mV lower than the drain pin voltage an overload of the
external MOS is detected and the timer capacitor will be loaded. After reaching a voltage at pin CT higher
than the timer threshold VThi the influenced channel is switched off. In this case the overload is stored in
the timer capacitor.
The timer capacitor will be discharged with a ’High’ signal at the input (see Fig. 1). After reaching the lower
timer threshold VTLo the overload protection is reset and the channel is able to switch on again.
7/13
L9380
Figure 3. Comparator hysteresisThe application diagram is shown in Fig. 4. Because of the transients present at the power lines during
operation and possible disturbances in the system the external resistors are necessary.
Positive ISO-Pulses at Drain, Gate Source are clamped with an active clamping structure. The clamping
voltage is less than 60V. Negative Pulses are only clamped with the ESD-Structure less than -15V. This
transients lower than -15V can influence the other channels.
In order to protect the transistor against overload and gate breakdown protection diodes between gate and
source and gate and drain has to be connected. In case of overvoltage into VS (VS > 20V) the charge pump
oscillation is stopped.
Then the charge pump capacitor will be loaded by a diode and a resistor in series up to VS (see Block
Diagram). In this case the channels are not influenced. In reverse battery condition the pins D1, D2, S1,
S2 follow the battery potential down to -13V (high impedance) and the gate driver pins G1, G2 is referred
to S1, S2. In this way it is assured that M1 and M2 will not be driven into the linear conductive mode. This
protection function is operating for VS1, VS2 down to -15V. The gate driver output G3 is referred to the D1
in this case. This function guarantees that the source to source connected N-Channel MOS transistors M3
and M4 remains OFF.
All the supplies and the in- and output of the PCBoard are supplied with a 40 wires flat cable (not used
wires are left open). This cable is submitted to the RF in the strip-line like described in DIN 40839-4 or ISO
The measured circuit was build up on a PCB board with ground plane. In the frequency range from 1MHz
to 400MHz and 80% AM-modulation of 1KHz with field strength of 200V/m no influence to the basic func-
tion was detected on a typical device.
The failure criteria is an envelope of the output signal with 20% in the amplitude and 2% in the time.
