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L7203STN/a3949avaiSMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATED


L7203 ,SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATEDBLOCK DIAGRAMPRSSRCLOW VOLTAGEDETECTORAGNDDGNDApril 20011/13L7203 (continued)DESCRIPTIONSMOOTH DRIV ..
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L7203
SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATED
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SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE
APPLICATION WITH POWER INTEGRATED
SMOOTH DRIVETM SYSTEM
1.8A DRIVE PEAK CAPABILITY
SLEW RATE CONTROL
INDUCTIVE SENSE START-UP ROUTINE
THERMAL SHUTDOWN
SUITABLE FOR 5V AND 12V APPLICATION
ONLY ONE HALL SENSOR IS REQUIRED
DESCRIPTION
The L7203 SPINDLE MOTOR IC includes a three
phase brushless spindle motor controller and the
power stage in switching mode. The device is de-
signed for both 5V and 12V OPTICAL DRIVE ap-
plication requiring up to 1.8A peak of current.
The device is realized in BCD5, a 0.7 pm Mixed
technology.
The spindle motor position detection is carried
out by means of a single comparator with hyster-
esis. In the start-up phase the "inductive sense
BLOCK DIAGRAM
ORDERING NUMBERS: L7203 (SO20)
L7203S ($8024)
start up method" is used to detect the rotor posi-
tion, determining the direction of starting rotation.
This procedure is implemented by a logic circuit
on chip.
The device applies three sinusoidal voltages to
the motor coils.
This is obtained through the application of the
MEMORY AND
VCC MEMORY SCAN
FREQUENCY
MULTIPLIER
H+ ROTOR
POSTION
H- DETECTOR
INDUCTIVE SENSE
STB START UP BLOCK
HA_,L . '
SUQPLY Halleas
DEGITAL PWM
MULTIPLIER
CONVER'ER
3WMOUTA
PWMOUTB
PWMOUTF
THERMAL
SHUTDOWN VM
POWER U
SECTION
LOW VOLTAGE
DETECTOR
CURRENT
LIMITER
April 2001
DESCRIPTION (continued)
SMOOTH DRIVING concept.
It is based on the idea of driving the motor wind-
ing through 3 sinusoidal voltages dephased of
120 degrees. The motor is controlled in voltage
mode, so no current control compensation net-
work is required.
Each profile is digitally described by 36 bytes
stored in a ROM memory.
These sinusoidal signals are modulated by multi-
plying each sample by a value stored in the KVAL
register. Using this kind of profiles it is possible to
obtain great advantages such as torque ripple
and acoustic noise reduction and lower EMI. An
easier track following is ensured, since vibration
are reduced.
The clock signal on the chip can be synchronized
to the external application clock signal.
An internal circuit can limit the current. The
threshold is fixed with a internal 0.2 V reference.
PIN CONNECTIONS
The device generates:
- a current generator to define output voltage
slew rate
- a 3.3 V reference to bias hall sensor.
- the HFG open drain output signal for speed
regulation.
The device includes :
- a circuit for thermal shutdown with hysteresis.
- a low voltage detector
In the STANDBY state the main functions of the
device are turned off, in order to minimize the
power consumption.
The STANDBY state of the device is imposed by:
- Thermal shutdown
- stand by signal from WP
SO20 $3024
PRS 1 STB
STB 1 FSYS
N.C. 2 FSYS
PRS 2 HFG
NC. 3 HFG
VM 3 SRC
VM 4 SRC
U 4 DGND U 5 DGND
V 5 AGND V 6 AGND
W 6 VCC N.C. 7 Vcc
RF 7 ISR W 8 ISR
RF1 8 HBIAS RF 9 H BIAS
H+ 9 PHS N.C. 10 PHS
H- 1 PWMIN RFI 11 PWMIN
D98IN928A H+ 1 2 H-
0011mm
2/13 Fi
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