L6751 ,Digitally Controlled Dual PWM for Intel VR12 and AMD SVIElectrical characteristics . . . . . . 154 Device configuration and pinstrapping tables . . . ..
L6751B ,Digitally Controlled Dual PWM for Intel VR12 and AMD SVIElectrical characteristics . . . . . . 164 Device configuration and pinstrapping tables . . . ..
L6756D ,2/3/4 phase buck controller for VR10, VR11.1 and AM2 processor applicationsElectrical characteristics . . . . . . 124 Device description and operation . . . . . 195 O ..
L6758A ,High Performance (4+1) Dual Controller for VR12Electrical characteristics . . . . . . 124 VR12 serial data bus and IC configuration . . . . ..
L6758ATR ,High Performance (4+1) Dual Controller for VR12Features programmable operation for multi-phase sections and a single-phase with independent contro ..
L6759D ,3+1 dual controller for VR12 with PMBusElectrical characteristics . . . . . . 134 Device configuration and pin-strapping tables . . ..
LC4064V-75TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-75TN44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064ZC-75M56I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064ZC-75MN132C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064ZC-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
LC4064ZC-75TN48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6751
Digitally Controlled Dual PWM for Intel VR12 and AMD SVI
November 2012 Doc ID 023992 Rev 1 1/59
L6751Digitally controlled dual PWM for Intel VR12 and AMD SVI
Datasheet − production data
Features VR12 compliant with 25 MHz SVID bus rev. 1.5 SerialVID with programmable IMAX,
TMAX, VBOOT, ADDRESS AMD SVI compliant Second generation LTB Technology® Flexible driver/DrMOS support JMode support Fully configurable through PMBus™ Dual controller: up to 6 phases for CORE and memory 1 phase for graphics (GFX), system agent
(VSA) or Northbridge (VDDNB) Single NTC design for TM, LL and Imon
thermal compensation (for each section) VFDE and GDC - gate drive control for
efficiency optimization DPM - dynamic phase management Dual remote sense; 0.5% Vout accuracy Full-differential current sense across DCR AVP - adaptive voltage positioning Dual independent adjustable oscillator Dual current monitor Pre-biased output management Average and per-phase OC protection OV, UV and FB disconnection protection Dual VR_RDY WLPGA72 6x6 mm package
Applications High-current VRM / VRD for desktop / server /
workstation Intel® / AMD CPUs DDR3 memory supply
DescriptionThe L6751 is a universal digitally controlled dual
PWM DC-DC designed to power Intel’s VR12 and
AMD SVI processors and memories: all required
parameters are programmable through dedicated
pinstrapping and PMBus interface. The device
features up to 6-phase programmable operation
for multi-phase sections and a single-phase with
independent control loops. When configured for
memory supply, single-phase (VTT) reference is
always tracking multi-phase (VDDQ) scaled by a
factor of 2. The L6751 supports power state
transitions featuring VFDE, programmable DPM
and GDC maintaining the best efficiency over all
loading conditions without compromising transient
response. The device assures fast and
independent protection against load overcurrent,
under/overvoltage and feedback disconnections.
The device is available in WLPGA72 6x6 mm
package.
Table 1. Device summary
Contents L67512/59 Doc ID 023992 Rev 1
Contents Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 51.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 72.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Device configuration and pinstrapping tables . . . . . . . . . . . . . . . . . . . 214.1 JMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Programming HiZ level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.1 Multi-phase section - phase # programming . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Multi-phase section - current reading and current sharing loop . . . . . . . . 30
6.3 Multi-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4 Single-phase section - disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5 Single-phase section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.6 Single-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.7 Dynamic VID transition support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.7.1 LSLESS startup and pre-bias output . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.8 DVID optimization: REF/SREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . 367.1 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2 Overcurrent and current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.1 Multi-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
L6751 ContentsDoc ID 023992 Rev 1 3/59
7.2.2 Overcurrent and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.3 Single-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Single NTC thermal monitor and compensation . . . . . . . . . . . . . . . . . 418.1 Thermal monitor and VR_HOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2 Thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.3 TM/STM and TCOMP/STCOMP design . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.1 Dynamic phase management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2 Variable frequency diode emulation (VFDE) . . . . . . . . . . . . . . . . . . . . . . 44
9.2.1 VFDE and DrMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3 Gate drive control (GDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4711.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.2 LTB Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PMBus support (preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5012.1 Enabling the device through PMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2 Controlling Vout through PMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.3 Input voltage monitoring (READ_VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.4 Duty cycle monitoring (READ_DUTY) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.5 Output voltage monitoring (READ_VOUT) . . . . . . . . . . . . . . . . . . . . . . . . 55
12.6 Output current monitoring (READ_IOUT) . . . . . . . . . . . . . . . . . . . . . . . . 55
12.7 Temperature monitoring (READ_TEMPERATURE) . . . . . . . . . . . . . . . . . 55
12.8 Overvoltage threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
List of tables L6751
4/59 Doc ID 023992 Rev 1
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Phase number programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. IMAX, SIMAX pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. ADDR pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. BOOT / TMAX pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. DPM pinstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. GDC threshold definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. L6751 protection at a glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Multi-phase section OC scaling and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 16. Supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 17. OV threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 18. L6751 WPLGA72 6x6 mm mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
L6751 List of figures
Doc ID 023992 Rev 1 5/59
List of figures
Figure 1. Typical 6-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. L6751 pin connections (left: top view - right: bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. JMode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6. Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7. Current reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. LSLESS startup: enabled (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. LSLESS startup: disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. DVID optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Output current vs. switching frequency in PSK mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. Efficiency performance with and without enhancements (DPM, GDC). . . . . . . . . . . . . . . . 45
Figure 14. ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right) . . . . . . . . . . . . . . . . 46
Figure 15. Equivalent control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. Control loop bode diagram and fine tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. Device initialization: PMBus controlling Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 18. L6751 WPLGA72 6x6 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
