L6711 ,3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACsFEATURESFigure 1. Package■ 2A INTEGRATED GATE DRIVERS■ FULL DIFFERENTIAL CURRENT READING ACROSS IND ..
L6711TR ,3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACsBlock DiagramOUTEN OUTENHS1 HS1 HS2 LS2 HS3 LS3 12.5µA OVPLOGIC PWM LOGIC PWM LOGIC PWMOVPADAPTIVE ..
L6712 ,TWO-PHASE INTERLAVED DC/DC CONTROLLERBLOCK DIAGRAMO OS SC / C / I IN NH H S SG GN ND D V VCCDR CCDRB BOOT OOT1 1BA BAN ND D- -G GAP AP H ..
L6712A ,TWO-PHASE INTERLEAVED DC/DC CONTROLLERBLOCK DIAGRAMO OS SC / C / I IN NH H S SG GN ND D V VCCDR CCDRB BOOT OOT1 1BA BAN ND D- -G GAP AP H ..
L6712AD ,TWO-PHASE INTERLAVED DC/DC CONTROLLER L6712L6712ATWO-PHASE INTERLEAVED DC/DC CONTROLLER■ 2 PHASE OPERATION WITH SYNCHRONOUS RECTIFIER CO ..
L6712ADTR ,TWO-PHASE INTERLAVED DC/DC CONTROLLERapplications.■ NON-LATCHED UNDERVOLTAGE PROT. Output voltage can be programmed through the in-tegra ..
LC4064B-75TN48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-10T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-25T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-25TN100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-5T48I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-5TN100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6711-L6711TR
3 PHASE CONTROLLER WITH DYNAMIC VID AND SELECTABLE DACs
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L6711November 2004
1FEATURES 2A INTEGRATED GATE DRIVERS FULL DIFFERENTIAL CURRENT READING
ACROSS INDUCTOR OR LOW-SIDE
MOSFET 0.5% OUTPUT VOLTAGE ACCURACY 6 BIT PROGRAMMABLE OUTPUT FROM
0.8185V TO 1.5810V IN 12.5mV STEPS 5 BIT PROGRAMMABLE OUTPUT FROM
0.800V TO 1.550V IN 25mV STEPS DYNAMIC VID MANAGEMENT ADJUSTABLE REFERENCE VOLTAGE
OFFSET 3% ACTIVE CURRENT SHARING
ACCURACY DIGITAL 2048 STEP SOFT-START PROGRAMMABLE OVERVOLTAGE
PROTECTION INTEGRATED TEMPERATURE SENSOR CONSTANT OVER CURRENT PROTECTION OSCILLATOR INTERNALLY FIXED AT
150kHz (450kHz RIPPLE) OSCILLATOR EXTERNALLY ADJUSTABLE OUTPUT ENABLE INTEGRATED REMOTE SENSE BUFFER TQFP48 7x7 PACKAGE WITH EXPOSED PAD
2APPLICATIONS HIGH CURRENT VRM/VRD FOR DESKTOP /
SERVER / WORKSTATION CPUs HIGH DENSITY DC/DC CONVERTERS
3DESCRIPTIONThe device implements a three phase step-down
controller with a 120° phase-shift between each
phase with integrated high current drivers in a
compact 7x7mm body package with exposed pad.
The device embeds selectable DAC: the output
voltage ranges from 0.8185V to 1.5810V with
12.5mV steps (VID_SEL=OPEN) or from 0.800V
to 1.550V with 25mV steps (VID_SEL=GND; VID5
drives an optional +25mV offset) managing dy-
namic VID with 0.5% accuracy over line and temp
variations. Additional programmable offset can be
added to the voltage reference with a single exter-
nal resistor.
The device assures a fast protection against load
over current and load over/under voltage. An inter-
nal crowbar is provided turning on the low side
mosfet if an over-voltage is detected.
In case of over-current, the system works in Con-
stant Current mode until UVP.
Selectable current reading adds flexibility in sys-
tem design.
3 PHASE CONTROLLER WITH DYNAMIC VID
AND SELECTABLE DACs
Rev. 2
L6711
Figure 2. Block Diagram
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
3/38
L6711
Figure 3. Pin Connections (Top view)
Table 4. Pin Function
L6711
Table 4. Pin Function (continued)
5/38
L6711
Table 4. Pin Function (continued)
L6711
Electrical Characteristcs (VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified)
Table 4. Pin Function (continued)
7/38
L6711
Electrical Characteristcs (continued)(VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified)
L6711
Electrical Characteristcs (continued)(VCC=12V±15%, TJ = 0°C to 70°C unless otherwise specified)
9/38
L6711(*) Since the VIDx pins program the maximum output voltage, according to VRD 10.x specs, the device automatically regulates to a voltage
19mV lower avoiding use of any external component to lower the regulated voltage. This improves the system tolerance performance since
the reference already offset is trimmed during production within ±0.5%.
Table 5. Voltage IDentification (VID) Codes.
L6711
Table 6. Voltage IDentification (VID) Codes.
11/38
L6711
Figure 4. PRINCIPLE SCHEMATIC 1 Low Side Mosfet Current Sense
L6711
Figure 5. PRINCIPLE SCHEMATIC 2 Inductor Current Sense
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L6711 DEVICE DESCRIPTIONThe device is a three phase PWM controller with embedded high current drivers that provides complete
control logic and protections for a high performance step-down DC-DC voltage regulator optimized for ad-
vanced microprocessor power supply. Multi phase buck is the simplest and most cost-effective topology
employable to satisfy the increasing current demand of newer microprocessors and modern high current
DC/DC converters and POLs. It allows distributing equally load and power between the phases using
smaller, cheaper and most common external power mosfets and inductors. Moreover, thanks to the 120°
of phase shift between each phase, the input and output capacitor count results in being reduced. Phase
interleaving causes in fact input rms current and output ripple voltage reduction and show an effective out-
put switching frequency increase: the 150kHz free-running frequency per phase, externally adjustable
through a resistor, results tripled on the output.
The controller includes multiple DACs, selectable through an apposite pin (VID_SEL), allowing compati-
bility with both VRD 10.x and Hammer specifications, also performing D-VID transitions accordingly. The
output voltage can be precisely selected, programming the VID and VID_SEL pins, from 0.8185V to
1.5810V with 12.5mV binary steps (VRD 10.x compliant mode - 6 BIT with -19mV offset already pro-
grammed during production) or from 0.800V to 1.550V with 25mV steps (VRM Hammer compliant mode
- 5 BIT, VID5 programs a 25mV positive offset in this case), with a maximum tolerance on the output reg-
ulated voltage of ±0.5% (±0.6% for Hammer) over temperature and line voltage variations.
The device permits easy and flexible system design by allowing current reading across either inductor or
low side mosfet in fully differential mode simply selecting the desired way through the CS_SEL pin. In both
cases, also a sense resistor in series to the related element can be considered to improve reading preci-
sion. The current information read corrects the PWM output in order to equalize the average current car-
ried by each phase limiting the error at ±3% over static and dynamic conditions unless considering the
sensing element spread.
The device provides a programmable Over-Voltage protection to protect the load from dangerous over
stress and can be externally set to a fixed voltage through an apposite resistor or it can be set internally
with a fixed percentage, latching immediately by turning ON the lower driver and driving high the FAULT
pin. Furthermore, preliminary OVP protection also allows the device to protect load from dangerous OVP
when VCC is not above the UVLO threshold.
Over-Current protection provided, with an OC threshold for each phase, causes the device to enter in con-
stant current mode until the latched UVP. Depending on the reading mode selected, the device keeps con-
stant the peak (inductor sensing) or the valley (LS sensing) of the inductor current ripple.
The device drives high the FAULT pin after each latching event: to recover it is enough to cycle VCC or
the OUTEN pin.
A compact 7x7mm body TQFP48 package with exposed thermal pad allows dissipating the power to drive
the external mosfet through the system board.
CURRENT READING AND CURRENT SHARING CONTROL LOOPThe device embeds a flexible, fully-differential current sense circuitry that is able to read across both low
side or inductor parasitic resistance or across a sense resistor placed in series to that element. The fully-
differential current reading rejects noise and allows placing sensing element in different locations without
affecting the measurement's accuracy. The kind of sense element can be simply chosen through the
CS_SEL pin: setting this pin free, the LS mosfet is used while shorting it to SGND, the inductor will be used
instead. Details about connections are shown in Figure 6.
The high bandwidth current sharing control loop allows current balance even during load transients: a cur-
rent reference equal to the average of the read current (IAVG) is internally built and the error between the
read current and this reference is converted to a voltage that with a proper gain is used to adjust the duty
cycle whose dominant value is set by the voltage error amplifier.
L6711
Figure 6. Current Reading Connections selectable through CS_SEL pin.
5.1 LOW SIDE Current Reading Leaving CS_SEL pin OPEN, the current flowing trough each phase is read using the voltage drop across
the low side mosfets RdsON or across a sense resistor in its series and it is internally converted into a cur-
rent. The transconductance ratio is issued by the external resistor Rg placed outside the chip between
CSx- and CSx+ pins toward the reading points (see Figure 7 right). The proprietary current sense circuit
tracks the current information for a time TTRACK = TSW/3 (TSW = 1/FSW) centered in the middle of the low-
side mosfet conduction time (OFF Time, see Figure 7 left) and holds the tracked information during the
rest of the period.
This device sources a constant 50µA current from the CSx+ pin: the current reading circuitry uses this pin
as a reference and the reaction keeps the CSx- pin to this voltage during the reading time (an internal
clamp keeps CSx+ and CSx- at the same voltage sinking from the CSx- pin the necessary current during
the hold time; this is needed when LS mosfet RdsON sense is implemented to avoid absolute maximum
rating overcome on CSx- pin). The current that flows from the CSx- pin is then given by the following equa-
tion (See Figure 7 - right):
where
RdsON is the on resistance of the low side mosfet and Rg is the transconductance resistor used between
CSx- and CSx+ pins toward the reading points; IPHASEx is the current carried by the relative phase and
IINFOx is the current information signal reproduced internally.
50µA offset allows negative current reading, enabling the device to check for dangerous returning current
between the phases assuring the complete current equalization. From the current information of each
phase, information about the total current delivered (IDROOP = IINFO1 + IINFO2 + IINFO3) and the average
current for each phase (IAVG = (IINFO1 + IINFO2 + IINFO3)/3 ) is taken. IINFOX is then compared to IAVG to give
the correction to the PWMx output in order to equalize the current carried by the three phases.
Figure 7. Current reading across LS mosfet: timing (left) and circuit (right) for each phase. CSx- 50µA R dsONg
------------------I PHASEx⋅+ 50µAI INFOx+== I INFOx dsONg
------------------I PHASEx⋅=
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L6711
5.2 INDUCTOR CURRENT READINGShorting CS_SEL pin to SGND, the current flowing trough each phase is read using the voltage drop
across the output inductor or across a sense resistor (RSENSE) in its series and internally converted into a
current. The transconductance ratio is issued by the external resistor Rg placed outside the chip between
CSx- and CSx+ pins toward the reading points (see Figure 6 right).
The current sense circuit always tracks the current sensed and still sources a constant 50µA current from
the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this voltage. To correctly reproduce
the inductor current an R-C filtering network must be introduced in parallel to the sensing element.
The current that flows from the CSx- pin is then given by the following equation (See Figure 8):
Where IPHASEx is the current carried by the relative phase.
Considering now to match the time constant between the inductor and the R-C filter applied (Time con-
stant mismatches cause the introduction of poles into the current reading network causing instability.
Moreover, it is also important for the load transient response and to let the system show resistive equiva-
lent output impedance), it results:
where
Where IINFOx is the current information reproduced internally.
50µA offset allows negative current reading, enabling the device to check for dangerous returning current
between the phases assuring the complete current equalization. From the current information of each
phase, information about the total current delivered (IDROOP = IINFO1 +IINFO2 + IINFO3) and the average cur-
rent for each phase (IAVG = (IINFO1 + IINFO2 + IINFO3)/3) is taken. IINFOX is then compared to IAVG to give the
correction to the PWM output in order to equalize the current carried by the three phases.
Since Rg is designed considering the OC protection, to allow further flexibility in the system design, the
resistor in series to CSx+ can be split in two resistors as shown in Figure 8.
Figure 8. Inductor Current Sense CSx- 50µA RLg
------- LL
-------⋅+ R gRC() Cg⋅⋅+--------- --------------- -------------- ----------⎜⎟⎜⎟⎜⎟⎛⎞ PHASEx⋅⋅+=L
------- R gRC() CgI CSx-≥⋅ 50µA RL--------I PHASEx⋅+ 50µAI INFOx+== = I INFOx I PHASExL--------⋅=
L6711 DAC SELECTION The device embeds a selectable DAC that allows the output voltage to have a tolerance of ±0.5% (0.6%
for Hammer DAC) recovering from offsets and manufacturing variations. The VID_SEL pin selects the
DAC table used to program the reference for the regulation as shown in Table 7.
Table 7. DAC SelectionVID pins are inputs of an internal DAC that is realized by means of a series of resistors providing a partition
of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the
set-point of the error amplifier, VPROG). Internal pull-ups are provided (realized with a 5µA current gener-
ator up to 3V Typ); in this way, to program a logic "1" it is enough to leave the pin floating, while to program
a logic "0" it is enough to short the pin to SGND.
Programming the "11111x" code (NOCPU, VID5 is irrelevant), the device shuts down: all mosfets are
turned OFF and SS_END is shorted to SGND. Removing the code causes the device to restart.
The voltage identification (VID) pin configuration also sets the Over / Under Voltage protection (OVP/UVP)
thresholds.
REMOTE VOLTAGE SENSEThe device embeds a Remote Sense Buffer to sense remotely the regulated voltage without any additional
external components. In this way, the output voltage programmed is regulated between the remote buffer
inputs compensating motherboard or connector losses. The very low-offset amplifier senses the output
voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for
the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors.
Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode cou-
pling for any picked-up noise.
If remote sense is not required, it is enough connecting the resistor RFB directly to the regulated voltage:
VSEN becomes not connected and still senses the output voltage through the remote buffer. In this case
the FBG and FBR pins must be connected anyway to the regulated voltage (See Figure 9).
7.1 Warning:The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy (0.6% for the Ham-
mer DAC) on the output voltage when the RB is used: eliminating it from the control loop causes the reg-
ulation error to be increased by the RB offset worsening the device performances!
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L6711
Figure 9. Remote Buffer Connections VOLTAGE POSITIONINGOutput voltage positioning is performed by selecting the reference DAC and by programming the different
contributors to the IFB current (see Figure 10). This current, sourced from the FB pin, causes the output
voltage to vary according to the external RFB resistor: this allows programming precise output voltage vari-
ations depending on the sensed current (Droop Function) as well as offsets for the regulation.
The three contributors to the IFB current value are: Droop Function (green); Offset (red); Integrated Temperature Compensation (fuchsia).
Moreover, the embedded Remote Buffer allows to precisely programming the output voltage offsets and
variations by recovering the voltage drops across distribution lines.
The output voltage is then driven by the following relationship (IOFFSET sign depends on TC setting):
Figure 10. Voltage Positioning and Droop Function
8.1 DROOP FUNCTIONDroop function allows the device to satisfy the requirements of high performance microprocessors, reduc-
ing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output
capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current:
a static error proportional to the output current causes the output voltage to vary according to the sensed
current. As shown in figure 4-right, the ESR drop is present in any case, but using the droop function the
total deviation of the output voltage is minimized. OUT VID RFBIFB⋅– VID RFBI DROOPI OFFSETITC–± ()⋅–==
L6711 The information about the total current delivered (IDROOP) is sourced from the FB pin (see Figure 10): con-
necting a resistor between this pin and VSEN (i.e. the output voltage), the total current information flows
only in this resistor because the compensation network between FB and COMP has always a capacitor in
series (CF, see Figure 10). The voltage regulated is then equal to:
Where VID is the reference programmed through VIDx and VID_SEL (Only the IDROOP contribute to IFB
has been considered).
Since IDROOP depends on the current information about the three phases, the output characteristic vs. load
current is given by:
Where RSENSE is the chosen sensing element resistance (Inductor DCR or LS RdsON), IOUT is the output
current of the system and RDROOP is its equivalent output resistance (The whole power supply can be then
represented by a "real" voltage generator with a voltage value of VID and an equivalent series resistance
RDROOP).
RFB resistor can be also designed according to the RDROOP specifications as follow:
8.2 OFFSETThe OFFSET pin allows programming a positive or a negative offset (VOS) for the output voltage.
When the Integrated Thermal Sensor is disabled (TC = SGND) a resistor ROFFSET connected vs. SGND
increases the output voltage: since the pin is internally fixed at 1.240V, the current programmed by the
resistor ROFFSET is mirrored and then properly subtracted from the IFB current (see Figure 11) as follow
(Only the IOFFSET contribute to IFB has been considered):
Figure 11. Voltage Positioning with OffsetThe device will add the programmed offset VOS to the output programmed voltage (considering now also
the droop effect) subtracting the relative offset current from the feedback current IFB:
Offset resistor can be designed by considering the following relationship (RFB is fixed by the Droop effect): OUT VID RFBI DROOP⋅–= OUT VID RFBI DROOP⋅– VID RFB SENSE--- --------- ----------I OUT⋅⋅– VID R DROOPI OUT⋅–== =FB R DROOP Rg SENSE
--- -------------------⋅= OUT VID RFBI OFFSET⋅+ VID RFB 1.240V OFFSET
------------- ------------⎝⎠⎛⎞⋅+ VID VOS+== = OUT VID RFBIFB⋅– VID RFB I DROOPI OFFSET– () = VID RFBI OFFSET R DROOPI OUT⋅–⋅+⋅–==
19/38
L6711Offset automatically given by the DAC selection or by VID5 when VID_SEL=SGND differs from the offset
implemented through the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5%
error (±0.6% for the Hammer DAC) over load and line variations while implementing the same offset
through the OFFSET pin causes additional errors to be considered in the total output voltage precision.
When the Integrated Thermal Sensor is enabled (see Figure 12 and following section), the pin programs,
in the same way as before, a negative offset. This is to compensate the positive native offset introduced
by the ITS. The effect of the programmed offset on the output voltage results (IOFFSET is now added to IFB
and no more subtracted as before):
Offset resistor is designed to compensate the ITS native offset as described in the following section.
The Offset function can be disabled by shorting the pin to SGND.
Figure 12. Voltage Positioning with Integrated Thermal Sensor
8.3 INTEGRATED THERMAL SENSORCurrent sense elements have non-negligible temperature variations: considering either inductor or LS
mosfet sense, the sensing elements modify proportionally to varying temperature. As a consequence, the
sensed current is subjected to a measurement error that causes the regulated voltage to vary accordingly.
To recover from this temperature related error, a temperature compensation circuit is integrated into the
controller: the internal temperature is sensed and the droop current is corrected (according to a scaling
external resistor RTC) in order to keep constant the regulated voltage.
The ITS circuit subtracts from the IFB current a current proportional to the sensed temperature as follow
(see Figure 12, Only the IDROOP and ITC contributes to IFB have been considered):
where
where A and B are positive constants depending on the value of the external resistor RTC (see Figure 13),
TJ is the device junction temperature and TMOS is the mosfet (or the used sensing element) temperature.
The resistor RTC can be designed in order to zero the temperature influence on the output voltage at a
fixed current as follow: OFFSET 1.240VOS
------------------- RFB⋅= OUT VID RFBI OFFSET⋅– VID RFB
1.240 OFFSET
-------------- -----------⎝⎠⎛⎞⋅– VID VOS–== = OUT T,I OUT() VID RFB SENSET MOS() --------------- -------------------I OUTITCTJ()–⋅⋅–=TCTJ() 1TC
----------- AB TJ 25– ()⋅+ []⋅=
