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L6563STN/a59avaiAdvanced transition-mode PFC controller
L6563ASTN/a2500avaiAdvanced transition-mode PFC controller
L6563ATRSTMN/a12500avaiAdvanced transition-mode PFC controller
L6563TRST,N/a2500avaiAdvanced transition-mode PFC controller


L6563ATR ,Advanced transition-mode PFC controllerfeatures and the possibility to operate with the proprietary Fixed-Off-Time control, makes the devi ..
L6563H ,High voltage start-up transition-mode PFCblock diagram . . . . . . . 10Figure 4. IC consumption vs VCC . . . 15Figure 5. IC consum ..
L6563HTR ,High voltage start-up transition-mode PFCBlock diagram ::33B6767B002323=&'=&'+96+969FF9FF2212))12))&RQWURO&RQWURO,,FKDFKD ..
L6563S ,Enhanced transition-mode PFC controllerblock diagram . . . . . . . 10Figure 4. IC consumption vs VCC . . . 15Figure 5. IC consum ..
L6563STR ,Enhanced transition-mode PFC controllerBlock diagram ::33B6767B002323=&'=&'9FF9FF5815819ROWDJH9ROWDJH=HUR&XUU=HUR& ..
L6563TR ,Advanced transition-mode PFC controllerfeatures high impedance. If either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V o ..
LC4032B-75T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032C-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-10TN44I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-25TN48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-5T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs


L6563-L6563A-L6563ATR-L6563TR
Advanced transition-mode PFC controller
March 2007 Rev 4 1/39
L6563
L6563A

Advanced transition-mode PFC controller
Features
Very precise adjustable output overvoltage
protection Tracking boost function Protection against feedback loop failure
(Latched shutdown) Interface for cascaded converter's PWM
controller Input voltage feedforward (1/V2) Inductor saturation detection (L6563 only) Remote ON/OFF control Low (≤ 90µA) start-up current 5mA max. quiescent current 1.5% (@ TJ = 25°C) internal reference voltage -600/+800 mA totem pole gate driver with
active pull-down during UVLO SO14 package
Applications

PFC pre-regulators for: HI-END AC-DC adapter/charger Desktop PC, server, WEB server IEC61000-3-2 OR JEIDA-MITI compliant
SMPS, in excess of 350W
Table 1. Device summary

Figure 1. Block diagram
Contents L6563 - L6563A
2/39
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 T racking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 28
6.8 Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
L6563 - L6563A Description
3/39
1 Description

The device is a current-mode PFC controller operating in Transition Mode (TM). Based on
the core of a standard TM PFC controller, it offers improved performance and additional
functions.
The highly linear multiplier, along with a special correction circuit that reduces crossover
distortion of the mains current, allows wide-range-mains operation with an extremely low
THD even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise
(1.5% @TJ = 25°C) internal voltage reference. The stability of the loop and the transient
response to sudden mains voltage changes are improved by the voltage feedforward
function (1/V2 correction).
Additionally, the IC provides the option for tracking boost operation (where the output
voltage is changed tracking the mains voltage). The device features extremely low
consumption (≤ 90 µA before start-up and ≤ 5 mA running).
In addition to an effective two-step OVP that handles normal operation overvoltages, the IC
provides also a protection against feedback loop failures or erroneous output voltage
setting.
In the L6563 a protection is added to stop the PFC stage in case the boost inductor
saturates. This function is not included in the L6563A. This is the only difference between
the two part numbers.
An interface with the PWM controller of the DC-DC converter supplied by the PFC pre-
regulator is provided: the purpose is to stop the operation of the converter in case of
anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core
saturation) in the L6563 only and to disable the PFC stage in case of light load for the DC-
DC converter, so as to make it easier to comply with energy saving norms (Blue Angel,
EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote
ON/OFF control both in systems where the PFC pre-regulator works as a master and in
those where it works as a slave.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
to drive high current MOSFETs or IGBTs. This, combined with the other features and the
possibility to operate with the proprietary Fixed-Off-Time control, makes the device an
excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.
Figure 2. Typical system block diagram
Description L6563 - L6563A
4/39
1.1 Pin connection
Figure 3. Pin connection (top view)
1.2 Pin description
Table 2. Pin description
L6563 - L6563A Description
5/39
Table 2. Pin description (continued)
Absolute maximum ratings L6563 - L6563A
6/39 Absolute maximum ratings
3 Thermal data
Table 3. Absolute maximum ratings
Table 4. Thermal data
L6563 - L6563A Electrical characteristics
7/39
4 Electrical characteristics
Table 5. Electrical characteristics

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Electrical characteristics L6563 - L6563A
8/39
Table 5. Electrical characteristics (continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
L6563 - L6563A Electrical characteristics
9/39
Table 5. Electrical characteristics (continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Electrical characteristics L6563 - L6563A
10/39
(1), (2) Parameters tracking each other
(3) The multiplier output is given by:
(4) Parameters guaranteed by design, functionality tested in production.
Table 5. Electrical characteristics (continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)CS KM MULT V COMP 2.5– ()⋅
VVFF2------------------------- ------------------------------------⋅=
L6563 - L6563A Typical electrical performance
11/39 Typical electrical performance

Figure 4. Supply current vs supply voltage Figure 5. VCC Zener voltage vs TJ
Figure 6. IC consumption vs TJ Figure 7. Feedback reference vs TJ
Figure 8. Start-up & UVLO vs TJ Figure 9. E/A output clamp levels vs TJ
Typical electrical performance L6563 - L6563A
12/39
Figure 10. Static OVP level vs TJ Figure 11. Vcs clamp vs TJ
Figure 12. Dynamic OVP current vs TJ
(normalized value)
Figure 13. Current-sense offset vs
mains voltage phase angle
Figure 14. Delay-to-output vs TJ Figure 15. Ic latch-off level on current sense vs J (L6563 only)
L6563 - L6563A Typical electrical performance
13/39
Figure 16. Multiplier characteristics @ VFF = 1V Figure 17. ZCD clamp levels vs TJ
Figure 18. Multiplier characteristics @ VFF = 3V Figure 19. ZCD source capability vs TJ
Figure 20. Multiplier gain vs TJ Figure 21. VFF & TBO dropouts vs TJ
Typical electrical performance L6563 - L6563A
14/39
Figure 22. TBO current mismatch vs TJ Figure 23. RUN thresholds vs TJ
Figure 24. TBO-INV current mismatch vs
TBO currents
Figure 25. PWM_LATCH high saturation vs TJ
Figure 26. TBO clamp vs TJ Figure 27. PWM_STOP low saturation vs TJ
L6563 - L6563A Typical electrical performance
15/39
Figure 28. PFC_OK thresholds vs TJ Figure 29. UVLO saturation vs TJ
Figure 30. Start-up timer vs TJ Figure 31. Gate-drive output low saturation
Figure 32. Gate-drive clamp vs TJ Figure 33. Gate-drive output high saturation
Application information L6563 - L6563A
16/39
6 Application information
6.1 Overvoltage protection

Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider.
Neglecting the ripple components, under steady state conditions the current through R1
equals that through R2. Considering that the non-inverting input of the error amplifier is
internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then:
Equation 1

If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5V
by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant. Then the current through R2 remains equal to
2.5/R2 but that through R1 becomes:
Equation 2

The difference current ∆IR1 = I’R1 - I’R1 = ∆VO/R1 will flow through the compensation network
and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it
reaches about 18 µA the output voltage of the multiplier is forced to decrease, thus reducing
the energy drawn from the mains. If the current exceeds 20 µA, the OVP is triggered
(Dynamic OVP), and the external power transistor is switched off until the current falls
approximately below 5 µA. However, if the overvoltage persists (e.g. in case the load is
completely disconnected), the error amplifier will eventually saturate low hence triggering an
internal comparator (Static OVP) that will keep the external power switch turned off until the
output voltage comes back close to the regulated value. The output overvoltage that is able
to trigger the OVP function is then:
Equation 3

∆VO = R1 · 20 · 10-6R2 IR1 2.5-------- VO 2.5–----------------------== =R1O 2.5– VO∆+----------- -----------------------------=
L6563 - L6563A Application information
17/39
An important advantage of this technique is that the overvoltage level can be set
independently of the regulated output voltage: the latter depends on the ratio of R1 to R2,
the former on the individual value of R1. Another advantage is the precision: the tolerance of
the detection current is 15%, which means 15% tolerance on the ∆VO. Since it is usually
much smaller than Vo, the tolerance on the absolute value will be proportionally reduced.
Example: VO = 400V , ∆VO = 40V.
Then: R1 = 40V/20µA = 2MΩ ; R2 = 2.5·2MΩ·/(400-2.5) = 12.58kΩ.
The tolerance on the OVP level due to the L6563/A will be 40·0.15 = 6 V, that is ± 1.36%.
When either OVP is activated the quiescent consumption is reduced to minimize the
discharge of the Vcc capacitor.
Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram
Application information L6563 - L6563A
18/39
6.2 Feedback Failure Protection (FFP)

The OVP function above described is able to handle "normal" overvoltage conditions, i.e.
those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the
overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails
open: the voltage loop can no longer read the information on the output voltage and will
force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise
with no control.
A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the
output voltage with a separate resistor divider (R3 high, R4 low, see Figure 34). This divider
is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset
value, usually larger than the maximum Vo that can be expected, also including worst-case
load/line transients.
Example: VO = 400 V, Vox = 475V. Select: R3 = 3MΩ;
then: R4 = 3MΩ ·2.5/(475-2.5) = 15.87kΩ.
When this function is triggered, the gate drive activity is immediately stopped, the device is
shut down, its quiescent consumption is reduced below 250 µA and the condition is latched
as long as the supply voltage of the IC is above the UVLO threshold. At the same time the
pin PWM_LA TCH is asserted high. PWM_LATCH is an open source output able to deliver
3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM
controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To
restart the system it is necessary to recycle the input power, so that the Vcc voltages of both
the L6563/A and the PWM controller go below their respective UVLO thresholds.
The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will
shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and
PWM_LA TCH keep their high impedance status. To restart the IC simply let the voltage at
the pin go above 0.26 V.
Note that this function offers a complete protection against not only feedback loop failures or
erroneous settings, but also against a failure of the protection itself. Either resistor of the
PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down
the IC and stopping the pre-regulator.
6.3 V oltage Feedforward

The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency fc of the overall open-loop gain because the gain
has a single pole characteristic. This leads to large trade-offs in the design.
For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means
having fc ≅ 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow
control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage Feedforward can compensate for the gain variation with the line voltage and allow
overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional
to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector)
and providing the resulting signal to the multiplier that generates the current reference for
the inner current control loop (see Figure 35).
L6563 - L6563A Application information
19/39
Figure 35. Voltage feedforward: squarer-divider (1/V
2 ) block diagram and transfer
characteristic

In this way a change of the line voltage will cause an inversely proportional change of the
half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of
the multiplier output will be halved and vice versa) so that the current reference is adapted to
the new operating conditions with (ideally) no need for invoking the slow dynamics of the
error amplifier. Additionally, the loop gain will be constant throughout the input voltage
range, which improves significantly dynamic behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small the voltage generated will be affected by a
considerable amount of ripple at twice the mains frequency that will cause distortion of the
current reference (resulting in high THD and poor PF); if it is too large there will be a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator's output voltage in response to large line
voltage changes. Clearly a trade-off is required.
The device realizes Voltage Feedforward with a technique that makes use of just two
external parts and that limits the feedforward time constant trade-off issue to only one
direction. A capacitor CFF and a resistor RFF , both connected from the VFF (pin 5) pin to
ground, complete an internal peak-holding circuit that provides a DC voltage equal to the
peak of the rectified sine wave applied on pin MULT (pin 3). RFF provides a means to
discharge CFF when the line voltage decreases (see Figure 35). In this way, in case of
sudden line voltage rise, CFF will be rapidly charged through the low impedance of the
internal diode and no appreciable overshoot will be visible at the pre-regulator's output; in
case of line voltage drop CFF will be discharged with the time constant RFF·CFF , which can
be in the hundred ms to achieve an acceptably low steady-state ripple and have low current
distortion; consequently the output voltage can experience a considerable undershoot, like
in systems with no feedforward compensation.
Application information L6563 - L6563A
20/39
The twice-mains-frequency (2·fL) ripple appearing across CFF is triangular with a peak-to-
peak amplitude that, with good approximation, is given by:
Equation 4

where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2·fL component, will be:
Equation 5

Figure 36 shows a diagram that helps choose the time constant RFF·CFF based on the
amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the
pin, the IC will not work properly if the pin is either left floating or connected directly to
ground.
Figure 36. RFF·CFF as a function of 3
rd harmonic distortion introduced in the input
current

The dynamics of the voltage feedforward input is limited downwards at 0.5V (see Figure 35),
that is the output of the multiplier will not increase any more if the voltage on the VFF pin is
below 0.5V . This helps to prevent excessive power flow when the line voltage is lower than
the minimum specified value (brownout conditions).FF∆ 2V MULTpk
14fLRFFCFF+---- -----------------------------------=3% 100
2πfLRFFCFF
---------------------------------=
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