L6452 ,DUAL 13 X 16 MATRIX HEAD INK JET DRIVERBlock Diagram16 POWER LINESPOWER &LOGICALSUPPLIES13 ADDRESS LINESCHANNEL APRINT HEADCONTROL PRINT H ..
L6506 ,CURRENT CONTROLLER FOR STEPPING MOTORSELECTRICAL CHARACTERISTICS (continued)COMPARATOR SECTION PERFORMANCE (Over Operating Temperature Ra ..
L6506D ,CURRENT CONTROLLER FOR STEPPING MOTORSL6506L6506DCURRENT CONTROLLER FOR STEPPING MOTORSDESCRIPTIONThe L6506/D is a linear integrated circ ..
L6506D013TR ,CURRENT CONTROLLER FOR STEPPING MOTORSABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage 10 VCCV Input Signals 7 ViP Tot ..
L6506D013TR ,CURRENT CONTROLLER FOR STEPPING MOTORSL6506L6506D®CURRENT CONTROLLER FOR STEPPING MOTORSDESCRIPTIONThe L6506/D is a linear integrated cir ..
L6506D013TR ,CURRENT CONTROLLER FOR STEPPING MOTORSELECTRICAL CHARACTERISTICS (continued)COMPARATOR SECTION PERFORMANCE (Over Operating Temperature Ra ..
LC36256AL-10 ,256 K (32768 words x 8 bits) SRAMFeatures• Access time70 ns (max.) : LC36256AL-70, LC36256AML-7085 ns (max.) : LC36256AL-85, LC362 ..
LC36256AML-10 ,256K (32768 words x 8 bits ) SRAMOrderlng number : EN4163Asynchronous Silicon Gate CMOS LSI/ LC36256AL, AML-70/85/10/12256 K (32768 ..
LC36256AML-12 ,256K (32768 words x 8 bits ) SRAMFeatures. Access time70 ns (max.) ,' LC36256AL-70. LC36256AML-7085 ns (max.) , M26256AU85, LC36256A ..
LC36256AML-70 ,256K (32768 words x 8 bits ) SRAMOrderlng number : EN4163Asynchronous Silicon Gate CMOS LSI/ LC36256AL, AML-70/85/10/12256 K (32768 ..
LC36256AML-85 ,256K (32768 words x 8 bits ) SRAMFeatures. Access time70 ns (max.) ,' LC36256AL-70. LC36256AML-7085 ns (max.) , M26256AU85, LC36256A ..
LC3664AML-10 , CMOS LSI 64K SRAM
L6452
DUAL 13 X 16 MATRIX HEAD INK JET DRIVER
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DUAL 13x16 MATRIX HEAD INK JET DRIVER
DRIVES TWO 13X16 MATRIX HEADS
HEAD TEMPERATURE SENSING
POWER UP SYSTEM
ELECTRICAL NOZZLE CHECK
8 BIT AID
5 BIT D/A
i 4KV ESD PROTECTED OUTPUTS
DESCRIPTION
L6452 is a device designed to drive two 13x16
matrix ink jet printheads in printer applications.
The output stage is able to source simultaneously
400 mA on each of the 16 power lines (columns)
with a duty cycle of 33% in normal printing and
66% in head pre-heating. On the address lines
(rows), the load is only capacitive (MOS FET driv-
ing capability). The driver can control two print-
heads, but only one is active at a time. The ad-
dress scanning counter is included and can be
disabled to allow a different scanning scheme.
Figure 1. Block Diagram
PQFP100
In order to avoid output activation during the sup-
ply transient, an internal power-up system is im-
plemented.
As supporting function, L6452 is capable of sens-
ing the head silicon temperature and to electri-
cally check each nozzle.
The device is also integrating a thermal protec-
16 POWER LINES
POWER &
LOGICAL =)
SUPPLIES I I
13 ADDRESS LINES
CONTROL PRINT HEAD CHANNEL A PRINT HEAD
LINES =) DRIVER , A
13 ADDRESS LINES
- CHANNEL B PRINT HEAD
AID & PRINT HEAD PRINT HEAD
TEMPERATURE :9 TEMPERATURE <
CONTROL LINES CONTROL
ANALOG D97IN523
INPUTS
March 1999
PIN CONNECTION (Top view)
LLI C) fl
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2 2 f, F 5 E a a 8 5 8 a d
tfifil8,er'2atr'lr'fJ,lgst,,g55trifi'sk't,,'a
O O I > > n: n: n: O > > > (D U) U I n: D U) 0
r-lr-Ti-li-li-lr-lr-lr-lr-lr-li-li-li-li-lr-lr-lr-li-Ir-li-l
/10099 98 97 96 95 94 93 92 9190 89 88 87 86 85 84 83 82 81 N
CRLATCH E 1 O 80 JENLC
OUTPUT15 E 2 79 J GND
Vc L 3 78 J HSA1
POWGND E 4 77 J HSA2
OUTPUT14 L 5 76 [l HSA3
OUTPUT13 E 6 75 [l HSA4
vc E 7 74 [l HSA5
OUTPUT12 L 8 73 [l HSAG
OUTPUT11 E 9 72 [l HSA7
Vc E 10 71 Cl HSA8
OUTPUT10 E 11 70 [] HSA9
OUTPUT9 E 12 69 Cl HSA10
Vc E 13 68 JHSA11
OUTPUT8 L 14 67 Cl HSA12
POWGND E 15 66 Cl HSA13
OUTPUT E 16 65 Cl v,
Vc E 17 64 Cl HSB13
OUTPUT6 E 18 63 Cl HSB12
OUTPUTS E 19 62 Cl HSB11
Vc E 20 61 [] HSB1O
OUTPUT4 E 21 60 Cl HSB9
OUTPUT3 E 22 59 Cl HSB8
Vc E 23 58 Cl HSB7
OUTPUT2 E 24 57 Cl HSB6
OUTPUT1 E 25 56 Cl HSB5
Vc E 26 55 Cl H884
POWGND E 27 54 Cl HSB3
OUTPUTO E 28 53 Cl HSB2
LATCH_CLEAR E 29 52 Cl HSB1
NCEN E 30 51 JGND
S:s132333435:ss:s7383940414243444546474849502
t_Jt_Jr_Jr_Jr_lr_lt_lt_Jt_Jt_Jt_Jr_Jr_Jr_Jt_lt_lt_Jt_lt_Jr_) Dg7l~4395
SQB$$EE§SEEE§§E¥EE¥E
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B fl E it 0 g
l 2 2 f]
PIN FUNCTIONS
Pin # Name Function
1 CRlatch A rising edge latches the information present into the control register
2, 5, 6, 8, 9, Output 15...0 High side DMOS outputs. To be active, Short Pulse and/or Long Pulse and Nozzle
11, 12, 14, Check Enable must have a low level
16, 18, 19,
21, 22, 24,
25, 28
3, 7, 10, 13, Vc Outputs Power Supply
17, 20, 23,
4, 15, 27, GND logic and powerground
51, 79, 92
29 Latch Clear A high level resets all bit in the latch
2/16 gr,
