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L6269STN/a960avai12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL "COMBO"


L6269 ,12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL "COMBO"BLOCK DIAGRAMCHARGE FREQUENCYSPINDLE SEQUENCERCS A OUT_APUMP LOCK LOOPCTAPBEMFB OUT_BPROCESSINGSTAR ..
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L6269
12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL "COMBO"
gerTpra'
12V DISK DRIVE SPINDLE & VCM, POWER
& CONTROL "COMBO"
GENERAL
" 12V (+/- 10%) OPERATION.
REGISTER BASED ARCHITECTURE
MINIMUM EXTERNAL COMPONENTS
BICMOS + VERTICAL DMOS (1.5mm)
VCM DRIVER
n 1.5A DRIVE CAPABILITY
0.9W TOTAL BRIDGE IMPEDANCE AT 25°C
LINEAR MODE
PHASE SHIFT MODULATION (PWM MODE)
INSTANTANEOUS, (GLICH FREE) SWITCH
BETWEEN THE 2 MODES
CLASS AB OUTPUT DRIVERS
ZERO CROSSOVER DISTORSION
14 BIT DAC DEFINE OUTPUT CURRENT
SELECTABLE TRANSCONDUCTANCE
4 PROGRAMMABLE PARKING VOLTAGE
DYNAMIC BRAKE
SPINDLE DRIVER
n 2.0A DRIVE CAPABILITY
u 0.8W TOTAL BRIDGE IMPEDANCE AT 25°C
I: BEMF, INTERNAL OR EXTERNAL, PROC-
ESSING
. SENSOR-LESS MOTOR COMMUTATION
. PROGRAMMABLE COMMUTATION PHASE
. LINEAR MODE AND CONSTANT TOFF PWM
OPERATION MODE
" INTERNAL FREQUENCY LOCKED LOOP
SPEED CONTROL (FLL)
BEMF RECTIFICATION DURING RETRACT
BUILT-IN ALIGNAMENT&GO START-UP
INDUCTIVE SENSING START UP OPTION
RESYNCHRONIZATION
DYNAMIC & REVERSE BRAKE
CONTROLLABLE OUTPUT SLEW RATE
OTHER FUNCTIONS
a 12V AND 5V MONITORING WITH EXTERNAL
SET TRIP POINTS AND HYSTERESIS
1: POWER UP/DOWN SEQUENCING
April 1999
PRODUCT PREVIEW
BICMOS TECHNOLOGY
TQFP44 (10x10mm)
ORDERING NUMBER: L6269
n LOW VOLTAGE SENSE
n 3.3V INPUT LOGIC COMPATIBILITY
. THERMAL SHUTDOWN AND PRETHERMAL
WARNING
DESCRIPTION
The L6269 integrates into a single chip both spin-
dle and VCM controllers as well as power stages.
The device is designed for 12V disk drive applica-
tion requiring up to 2.0A of spindle and 1.5A of
VCM peak currents.
A serial port with up to 25 MHz capability provides
easy interface to the microprocessor. A register
controlled Frequency Locked Loop (FLL) allows
flexibility in setting the spindle speed. Integrated
BEMF processing, digital masking, digital delay,
and sequencing minimize the number of external
components required.
Power On Reset (POR) circuitry is included. Upon
detection of a low voltage condition, POR is as-
serted, the internal registers are reset, and spin-
dle power circuitry is tri-stated. The BEMF is recti-
fed providing power for actuator retraction
followed by dynamic spindle braking.
The device is built in BICMOS technology allow-
ing dense digital/analog circuitry to be combined
with a high power DMOS output stage.
This is preliminary information on a new product now in development. Details are subject to change without notice.
BLOCK DIAGRAM
CHARGE
cs PUMP
SW1 DRIVER
FLL FILTER
SYS CLK
PWM/SLEW
FLL RES
SPN COMP
BRK CAP
FREQUENCY
LOCK LOOP SPINDLE SEQUENCER
PROCESSING
START-UP RSENSE
RE_SYNC
ZERO CROSS
DETECTION
ISENSE
DYNAMIC/
REVERSE
SPINDLE
CURRENT
CONTROL
PWM/LIN
REGISTERS VCM CURRENT
CONTROL PSM/LIN VCM_A+
PARKING
SERIAL
SCLK INTERFACE
TR_12V SUPPLY
TR_5V MONITORS
THERMAL
SUPPLY
14 BIT
CALIBRATION
RECTIFICATION
REFERENCE
VOLTAGE
VCM DAC
GENERATOR
vc M_A-
VCM_GND
SENSE-IN-
SENSE_IN+
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PIN CONNECTION
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f_| I_| l_| l_| l_| l_l i-l i-l i-l i-l i-l
44 43 424140 39 38 37 36 35 34\
FCOM E 1 O 33 [] SW1
CTAP L 2 32 [] FLL_RES
PWM/SLEW E 3 31 [] VCC
OUT_C E 4 30 [] VCM_A+
|_SENSE L 5 29 [l SENSE_IN-
R_SENSE l: 6 28 [l VCM_GND
OUT_B l: 7 27 [l SENSE_|N+
GND E 8 26 [l VCM_A-
R_SENSE L 9 25 [l VCC
OUT_A E 10 24 1 CS
INDEX E 11 23 1 CP
\ 12 13 14 15 16 17 18 19 20 21 22 /
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