L6238S-L6238SQA-L6238SQT Fast Delivery |IC PHOENIX CO.,LIMITED

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L6238S-L6238SQA-L6238SQT
12V SENSORLESS SPINDLE MOTOR CONTROLLER
L6238S
12V SENSORLESS SPINDLE MOTOR CONTROLLER
PRODUCT PREVIEW
12V OPERATION
3A, THREE-PHASE DMOS OUTPUT
(TOTAL Rdson 0.52Ω) HALL SENSORS REQUIRED
DIGITAL BEMF PROCESSING
LINEAR OR PWM CONTROL
STAND ALONE OR EXT. DRIVER
SHOOT-THROUGH PROTECTION
THERMAL SHUTDOWN
DESCRIPTION
The L6238Sisa Three-Phase, D.C. Brushless
Spindle Motor Driver system. This device features
both the Power and Sequence Sections.
Higher Power Applications can be activied with
the additionofan externalLinear Driver,orby op-
erating the InternalDriversin PWM.
Motor Start-Up, without the useof Hall Sensors,
canbe achieved eitherby an internal start-up al-
gorithmor by manually sequencing the Output
Drivers, usinga varietyof User-Defined Start-UP
Algorithms.
Protection features include Stuck Rotor\Backward
Rotation Detection and Automatic Thermal Shut-
down.
October 1995
ZERO
CROSSING
DETECTOR
ALIGN+GO
START-UP
ONE-SHOT
SLEW-CTRL
PWM
LINVL
THERMAL
SHUTDOWMOT-WARN
CHARGE
PUMP
CPUMP3
CPUMP1
CPUMP2
D95IN232
BIAS
POWER
STAGE
AV=4V/V
DIGITAL
DELAY OUTB
OUTC
CTRTAP
CSA INPUT
GND
PWM
TIM
VANALOG
BEMF
SENSE
VPOWER
BRAKE
DELAY
RSENSE1
DRV
CNTL
TDLY(0)
CSA
OUTA
GATE DRIVEGMCOMP
SYSTEM
CLOCKSYS CLOCK
RSENSE2
VCTRL
PWM
COMP
PWM/
SLEW
SEQUENCER
FALIGN
OUTPUT
ENABLE
RUN/
BRAKE
SEQ INCR
MONO/SEQ
CTRL
TDLY(1)
TDLY(2)
MONO
DET
MASKDLY
TOGGLE DIVIDE N
SPIN
SENSE
FMTRSELPOL
BLOCK DIAGRAM
ORDERING NUMBERS: L6238S (PLCC44)
L6238SQA (PQFP44)
L6238SQT (TQFP64)
PLCC44
PQFP44
TQFP64
1/31
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
BVdss Output Brakdown Voltage 17 V
VPower Motor Supply Voltage 15 V
VLogic Logic SupplyVoltage 7 V
VAnalog Analog Supply Voltage 15 V
Vin Input Voltage -0.3to7 V
Cstorage Charge Pump Storage Capacitor 4.7 μF
Imdc Motor Current (DC) (TQFP64 only)
(PLCC44 and PQFP44)
Impk Peak Motor Current (Pulsed: Ton= 5ms, d.c.= 10%) 5 A
Ptot Power Dissipationat Tamb=50 °C(PLCC44)
(TQFP64)
(PQFP44)
1.3 Storage and Junction Temperature -40to 150 °C
THERMAL DATA
Symbol Parameter PLCC44 PQFP44 TQFP64 Unit
Rth(j-amb) Thermal Resistance Junction-Ambient 34 45 45 °C/W
Those Thermal Dataare validifthe packageis mountedon Mlayer boardin stillair235644142444322211918 20 2827262425
OUTPUT
SPIN
SENSE
BRAKE
DELAY
CHARGE
PUMP
GND RSENSE
GNDMASK
DELAY
VPOWERPWM/SLEWCENTER
TAP
GND
CHARGE PUMP1
CHARGE PUMP3
OUTPUTA
VANALOG
VPOWER
N.C.
TDLY(0)
TDLY(1)
TDLY(2)
GND
GND
GATE DRIVE COMP
OUTPUTC
CSA INPUT
RSENSE2
VCONTROL
N.C.
FMOTOR
VLOGIC
GND
RUN/BRAKE
OUTPUT
ENABLE
PWM/LINEAR
SELECT
POLE
OTWARN
PWM
LIMIT
TMR
PWM
COMP
FALIGN
MONO/SEQINC
CTRL
SEQ.
INCREMENT
SYSTEM
CLOCK
D95IN245
PIN CONNECTION PLCC44 (Top view)
L6238S
2/31
235647891042413938 40 4847464445OUTPUT
OUTPUT
N.C.VPOWERVANALOG VPOWER GNDGNDGNDCHARGE
PUMP
CHARGE
PUMP
N.C.
OTWARN
SELECT POLE
PWMLIMITTMR
OUTPUTENABLE
PWM/LINEAR
RUN/BRAKE
SEQ. INCREMENT
SYSTEM CLOCK
MONO/SEQINC CTRL
FALIGN
CHARGE PUMP2
RSENSE1
RSENSE1
BRAKE DELAY
OUTPUTB
SPIN SENSE
OUTPUTB
PWM/SLEW
CENTERTAP
VPOWER
VPOWER
OUTPUT
OUTPUT
N.C.
RSENSE
CSA
INPUT
RSENSE
GNDGNDGND
COMP
GATE
DRIVE
D95IN244
PWMCOMP
N.C.
GND
MASK DELAY
GND
GND
GND
N.C.
GND
GND13141516363433 35
TDLY(0)TDLY(1)GNDGND TDLY(2)
VCONTROL
FMOTOR
GNDGND
VLOGIC
PIN CONNECTION TQFP64 (Top view)235647891027262423 25 3332312930
VANALOGN.C.TDLY(0)TDLY(2)GND TDLY(1) GNDCHARGE
PUMP
CHARGE
PUMP
VPOWEROUTPUT
OTWARN
SELECT POLE
PWM LIMIT TIMER
PWM/LINEAR
RUN/BRAKE
OUTPUT ENABLE
SEQ. INCREMENT
SYSTEM CLOCK
MONO/SEQINC CTRL
FALING
PWM COMP.
GND
CHARGE PUMP2
RSENSE1
BRAKE DELAY
OUTPUTB
SPIN SENSE
PWM/SLEW
CENTER TAP
VPOWER
MASK/DELAY
GND
CSA
INPUT
VCONTROL
N.C.
VLOGIC
GND
FMOTOR
GND
GATE
DRIVE
COMP
RSENSE
OUTPUT D95IN243
PIN CONNECTION PQFP44 (10x10) (Top view)
L6238S
3/31
PIN FUNCTIONS
PLCC44 PQFP44 TQFP64 Name I/O Function 39 56,57 OUTPUTB I/O DMOS Half Bridge Output and InputBfor Bemf sensing. 40 58 SPIN SENSE O Togglessat each Zero Crossingof the Bemf. 41 59 BRAKE DELAY I Energy Recovery timeconstant, definedby external R-Cto ground. 42 60,61 Rsense1 O Outputs A+B connectionsforthe Motor Current Sense Resistor ground 43 62 CHARGE
PUMP2 Negative Terminalof Pump Capacitor.7,
17,29,
39,40 11,
23, 33,
34,44 GROUND S Ground terminals. 2 4 CHARGEPUMP1 I Positive terminalof Pump Capacitor. 3 5 CHARGEPUMP3 O Positive terminalof Storage Capacitor. 4 6,7 OUTPUTA I/O DMOS Half Bridge Output and InputAfor Bemf sensing.
11,42 5,36 9, 10,
52,53
Vpower S Power Section Supply Terminal. 6 11 Vanalog S 12V supply.
13,32 7,26 8, 18,
19,31,
N.C N.C Open Terminal 8 12 Tdly(0) I Three bits thatsetthe Delay between the detectionofthe Bemf
zero crossing, andthe commutationofthe next Phase.15 9 13 Tdly(1) I 10 14 Tdly(2) I 12 20 OTWARN O Overtemperature Warning Output 13 21 SELECT POLE I Selects#of Motor Poles.A zero selects8, whilea one selects4
poles. 14 22 PWM TIMER I Capacitor connectedto thispin sets the maximum time allowed
for 100% duty cycle during PWM operation 15 23 PWM/LINEAR I Selects PWMor Linear Output Current Control 16 24 OUTPUT
ENABLE Tristates Power Output Stage whena logic zero. 17 25 SEQUENCE I Rising edge will initiate start-up.A Braking rountineis started
when this inputis brought low. 18 26 SEQ
INCREMENT A lowto high transitionon thispin increments the Output State
Sequencer. 19 27 SYSTEM CLK I Clock Frequencyforthe system timer/counters. 20 28 MONO/SEQ.
INC. CONTROL A logic one willdisablethe Monotonicity Detector and Sequence
Increment functions. 21 29 Falign I Reference Frequencyfor theopt. Auto-Start Algorithm.Ifint.
startupisnot used, thispin mustbe connectedto the System
Clock. 22 30 PWM COMP O Outputof the PWM Comparator 24 35 Vlogic S 5V Logic Supply Voltage. 25 36 Fmotor O Motor Once-per-Revolution signal. 27 37 Vcontrol I Voltageat this input controlshe Motor Current 28 38 CSA INPUT I Inputtothe Current Sense Amplifier. 29 39,40 Rsense2 O OutputC connectionforthe Motor Current Sense Resistorto
ground. 30 42,43 OUTPUTC I/O DMOS Half Bridge Output and InputCfor Bemf sensing. 31 44 gm COMP I A series RC networkto ground that definesthe compensationof
the Transconductance Loop.
L6238S
4/31
PIN FUNCTIONS
PLCC44 PQFP44 TQFP64 Name I/O Function 32 45 GATE DRIVER I/O Driversthe Ext. PFET Gate Driverfor Higher Power applications.
Thispin mustbe groundedifan external driveris not used. 35 51 MASK/DELAY O Internal Logic Signals usedfor production Testing 37 54 CENTER TAP I Motor Center Tap usedfor differential BEMF sensing. 38 55 PWM/SLEW I R/Cat this inputset the Linear Slew Rate and PWM OFF-Time
0.0 0.3 1.0 3.0 Cb(μF)0.0
TBD
(s)
D95IN274
Figure1: Brake Delay Timeoutvs Cbrake
(Rbrake= 1Meg) 30 100 300 Rs(KΩ)0.0
SVR
(V/μs)
D95IN275
Figure2: Linear Slew Ratevs Rslew
100 300 Coff(pF)1
PWM
(μs)
D95IN276
Figure3: PWM Off- Timevs Rslew/Coff
100 300 Ctimer(pF)10
PWM
(μs)
D95IN277
Figure4: PWM Limit Time- Outvs Ctimer
L6238S
5/31
ELECTRICAL CHARACTERISTICS (Tamb =0to 70°C; VA =VPwr= 12V; Vlogic= 5V; unless otherwise
specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
GENERAL
Vanalog Analog Supply Voltage 10.5 13.5 V
Ianalog Analog Supply Current Run ModeVA= 13.5V 1.5 2.7 4.5 mA
Brake ModeVA= 13.5V 280 800 μA
Vlogic Logic Supply Voltage 4.5 5.0 5.5 V
Ilogic Logic Supply Current Run Mode Vlogic= 5.5V 1 2 3.2 mA
Brake Mode 100 500 1000 μA
THERMAL SHUTDOWN
*Tsd Shut Down Temperature 150 180 °C
*Thys Recovery Temperature
Hysteresis °C
*Tew Early Warning Temperature Tsd-25 °C
POWER STAGE
RDS(on) Output ON Resistance per FET Tj =25°C;VA= 10.5V= 125°C;VA= 10.5V
0.20 0.26
Io(leak) Output Leakage Current Vpwr= 15V 1 mA Body Diode Forward Drop Im= 2.0A 1.5 V
dVo/dt Output Slew Rate (Linear) Rslew= 100KΩ 0.15 0.30 0.45 V/μs
Output Slew Rate (PWM) 10 150 V/μs
Igt Gate Drivefor Ext. Power
DMOS
Vcontrol= 1V; Vsns= 0V;= 10.5V
4.5 mA
VGate-Drive Ext Driver Disable Voltage 0.7 V
VCtrl-Range Voltage Control Input Range 0 5.0 V
Iin(VCtrl) Voltage Control Input Current 10 μA
PWM OFF-TIME CONTROLLER (Rslew= 100KΩ,Coff= 120pF)
Toff OFF Time 9 11 14 μs
Vchrg Capacitor Charge Voltage VA= 10.5V 2.31 2.65 3.1 V
Vtrip Lower Trip Threshold 1.25 V
PWM LIMIT TIMER
Ichrg Capacitor Charge Current VPWM Timer= 0V;VA= 10.5V 10.0 20.0 30 μA
Vchrg Capacitor Charge Voltage VA= 10.5V 3.0 3.5 4.0 mV
Vtrip Lower Trip Threshold 100 400 V
BEMF AMPLIFIER
ZinCT Center Tap Imput Impedance 20 30 40 KΩ
VBemf Minimum Bemf (Pk-Pk) 60 mV
CURRENT SENSE AMPLIFIER
Isnsin Input Bias Current VA= 13.5V 10 μA Voltage Gain 3.8 4.0 4.2 V/V Slew Rate 0.33 0.8 V/μs
L6238S
6/31
ELECTRICAL CHARACTERISTICS (Continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
BRAKE DELAY
Vchrg Capacitor Charge Voltage RT= 50K 8.8 9.6 10.5 V
Iin Input Current Vin= 5.0V 500 nA
Iout3 Source Current VA= 10.5V 0.5 mA
VThres Delay Timer Low TripThreshold 1.2 1.8 2.8 V
CHARGE PUMP
Vout Storage Capacitor Output
Voltage= 10.5V;Iout= 500μA17 V
Fcp Charge Pump Frequency 140 450 KHz
Iin Vstorage Input Current (Run
Mode)
Vstorage= 12V;VA =Vlogic=0 25 μA
Ibrkdly Vstorage LeakageCurrent
(Brake DelayMode)
Vstorage= 12V;VA =Vlogic=0 0.4 1 μA
Ibrake Vstorage LeakageCurrent
(Brake Mode)
Vstorage= 12V;VA =Vlogic=0 0.1 1 μA
SEQUENCE INCREMENT
tseq Time Between Rising Edges 1 μs
OUTPUT TRANSCONDUCTANCE AMPLIFIER Note: Measureat OTA Comp. pin.
Voh Voltage Output High VA= 10.5V 10 V
VoutL Output Voltage 2.0 V
Isource Output Voltage 40.0 0.5 V
Isink Output Sink Current 40.0 μA
LOGIC SECTION
VinH
VinL
Input Voltage (All Inputs
Except Run/Brake
Vlogic= 4.5to 5.5V 3.5
VinH
VinL
Run/Brake Input Voltage Vlogic= 4.5to 5.5V 2.0
IinH
IinL
Input Current
1.0 μA
VoutL
VinL
Output Voltage Vsink= 2.0mA
Vsource= 2.0mA 4.5
0.5 V
Fsys System Clock Frequency 8.0 12.0 MHz
toff/ton Clock ON/OFF Time 20 ns
Tdelay(2) Tdelay(1) Tdelay(0) Commutation Phase Delay, Electrical Degrees 0 1 2.0 0 0 9.4 1 1 18.80 1 0 20.68 0 1 22.56 0 0 24,44(*) 1 1 26.32 1 0 28.20
(*) Input Default
Phase Delay Truth Table
L6238S
7/31
FUNCTIONAL DESCRIPTION
1.0 INTRODUCTION
1.1 Typical Applicationa typical application, the L6238S will operatein
conjunction with the L6244 Voice Coil Driveras
shownin Fig. 1-1.
This configuration requiresa minimum amountof
external components.
1.2 Input Default States
Figure 1-2 depicts the two possible input struc-
tures for the logic inputs.Ifa particular pinis not
OUT
CTR
TAP
OUT
OUT
RSENSE
CSA
10nF 8
CHRG
PUMP
CHRG
PUMP
8.12MHz
CHRG
PUMP
SYS
CLK
ALIGN
PWR
11,42
400pF
PWM
SLEW
100K
10K
GM
COMP
BRK
DLY
6,7,17,
29,39,40
GND
60-90Hz Note:
the
internal
Start-up
Algorithm
not
used,
connect
this
pin
SYS_CLK
ANLG
12V
LOGIC
VLOGIC(5V)
L6238S
SPINDLE
MOTOR
DRIVER
CONTROLLER
220pF161514183134332322
GATE
DRV
MONO
SEQ.
OUT
ENA
RUN/BRKV
CTRL
SEQ
INC
MTR
WARM
DLY(0)
DLY(1)
DLY(2)
PWM TMR
data(0)
data(1)
data(2)
data(3)
data(4)
data(5)
data(6)
data(7)
10K
LOGIC
POR
GATE
DRIVE
Vpower
3.6K
27K
VCM
360K
360K
360K
10K
100K15
6,7,17,29,39,4041
GND
POR
DLY
RprogramV
PROG
CC/2
GAIN2-INDA0OutGAIN1-INERROR AMP
OUTPUT
PUMP
CP2
CP1
D95IN278
L6244
VOICE
COIL
DRIVER
DA2
OUT
SENSE
OUT
OUT
SENSE
+INPUT
SENSE
-INPUT
OUT
SENSE
Figure 1-1
L6238S
8/31
usedin an application,it may eitherbe connected groundor VLOGICas required,It may alsobe
simply left unconnected. no connectionis made, the pinis either pulled
highor low by internal constant current gener-
atorsas shown above. listingof the logic and clock inputsis shownin
Table1 with the correspondingdefault state.
1.3 Modesof Operation
There are5 basic modesof operation. Tristate
When Output Enableis low, the output power
drivers are tristated. Start-Up
With Output Enable high, bringing Run/Brake
froma lowtoa high will energize the motor and
the system will be drivenby the Fully-Integrated
StartUp Algorithm. user-defined Start-Up Algorithm, under controla MicroProcessor, can alsobe achieved via the
sequence increment input. Run
Run modeis achieved when the motor speed
(controlled by the external microprocessor)
reaches the nominal speed. Park
When Run/Brakeis brought low, energyto park
the heads maybe derived from the rectified Bemf.
The energy recovery timeisa functionof the
Brake Delay Time Constant.In this state, the qui-
escent currentof the deviceis minimized (sleep
mode). Brake
After the Energy Recovery Time-Out, the devicein Brake, withall lower Driversin full conduc-
tion.
There are two mutually exclusive conditions
which may be present during the Tristate Mode
(wake up):
a)the spindleis stopped.
b)the systemis still runningata speed that
allowsfor resynchronization. orderto minimize the rampup time, the micro-
controller has the possibilityto:
check the SPIN SENSE pin, (which togglesat
the Bemf zero crossing frequency)
enable the powerto the motor based on the
previous information. Otherwise the μP mayis-
suea Brake command, followedby the start- procedureafter the motor has stopped spin-
ning.
2.0 STATEDIAGRAMS
2.1 State Diagram
Figure 2-1isa complete State Diagramof the
controller depicting the operational flowasa func-
tionof the control pins and motor status. The flow
canbe separatedinto four distinct operations.
2.2 Align+ Go
Figure 2-2 represent the normal flow that will
achievea spin-upof the spindle motor using the
internally generated startup algorithm.
Upon power up, or from any state with
Run/Brake low the controller first sets the state
machinefor State=1 with the Outputs Tristated.
The period counter that monitors the time be-
tween zero crossingis stopped, analog with the
phase and mask delay counters.
When Run/Brakeis brought high, the motorisin
the first partof the align modeat State2 (Output high and OutputC low).If Output Enableis
high, the controller first checksto determineif the
motoris still spinning fora timeof 21Ω (with
Sys_Clk= 10MHz). The drivers are now enabled
and after the align time-out, (64/Falign), the se-
quencer double increments the outputsto State4
(OutputB high and OutputA low). The first part this align modeis usedto reduce the effectsof
stiction
Pin Function Configuration
Tdly (0,1,2) Pull-Down
Select Pole Pull-Down
PWM/Linear Pull-Down
Output Enable Pull-Down
Run/Brake Pull-Up
Sequence Increment Pull-Down
System Clock Pull-Up
Faling Pull-Up
Table1
VLOGIC
10μA
VLOGIC
10μA
PULL-UP PULL-DOWND95IN279
Figure 1-2
L6238S
9/31
After the next align time-out 192/Falign), the con-
troller enters the Go mode, were the sequencer
again double increments the output phase upon
detectionof the motor’s Bemf.
The align time-out maybe optimizedfor the appli-
cation by changing the Faling reference fre-
quency. Watch-Dog Timer protection featureis built into
the control logicto monitor the Falign pin fora
clocking signal. This circuitry, shownin Figure 2-3
will prevent start up the deviceif the Falign clock not present.
Without this feature, the output would remainin
the first phase under high current conditions,if
the clockwere not present. the external sequenceris usedto provide start
up, the system clock maybe tiedto the Falign pin satisfy the requirementsof the Watch-Dog
Timer.
2.3 Resynchronization poweris momentarily lost, the sequencer can
automatically resynchronize to the monitored
STATE=1
DRIVERSOFF
MINCLOCK DELAY
PERIODSTOP
DELAYSTOP
MASKSTOP
SEQLNC=1&
OUTENA=0
RUN/BRK=X INT.START-UPDISABLED
MIN.CLOCKDELAY
LOADMIN. DELAY
LOADMIN. MASK***
RUN/BRK=1&
OUTENA=1 DRIVERSON
PERIOD COUNT
DELAY COUNT
STATE=STATE+1*
MASKCOUNT MASKCOUNT
SEQINC=0 SEQINC=1
LOADDELAY=PERIOD
LOADMASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAY COUNT**
BEMF BEMFSEQINC=0 SEQINC=1
RUN/BRAKE=1
RUN/BRAKE=0
FROMANY STATE
DRIVERSOFF
MINCLOCK DELAY
LOADMINMASK***
PERIODSTOP
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
LOADMIN. DELAY
LOADMIN. MASK***
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
BEMF
STATE=STATE+1SEQINC=1 RETURNTO
PREVIOUSSTATE
(CHANGINGSEQINC=1)
BEMF FROM ANYSTATE
WITHSEQ_INC=0 VALIDIFSEQINC=0,ANDDELAYTIMESOUT
**CLOCKDELAY=F(TDLY_[2:0])
WHEN BEMFPERIOD <3.3ms@10MHz
(SPEED >12.7HzFOR8POLES)
STATE=STATE+2
CHECKFORZcBEMF
DRIVERSOFF
STATE=STATE+1
MIN CLOCKDELAY
LOADMINDELAY
LOADMAXMASK
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
OUTENA=1
OUTENA=1
OUTENA=1DRIVERSOFF
MIN CLOCKDELAY
PERIODSTOP
DRIVERSON
PERIODSTOP
DELAYSTOP
MASKSTOP
STATE=STATE+2
STATE=STATE+1
LOADDELAY=MIN
LOADMASK=MAX
PERIODCOUNT
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
BEMF
LOADDELAY=MIN
LOADMASK=MIN
RESETPERIOD
PERIOD COUNT
DELAYCOUNT*
STATE=STATE+1
MASKCOUNT
SYS_CLK
SYS_CLK
DRIVERSOFF
RUN/BRK=0
DRIVERSOFF
RUN/BRK=0
DRIVERSON
LOADDELAY=PERIOD
LOADMASK=PERIOD
RESETPERIOD
PERIOD COUNT
DELAYCOUNT*
STATE=STATE+1
MASKCOUNT
DRIVERSOFF
MINCLOCKDELAY
PERIODSTOP
OUTENA=0
BEMF
MONO=0**
BEMFOUTENA=1OUTENA=1
BEMF
ALIGN&
GOMODE
RESYNCHRONIZATION
MODE
RUN
MODE
*CLOCKDELAY=F(TDLY[2:0]WHENBEMFPERIOD <3.3ms@10MHz(SPEED>12.7HzFOR8 POLES)
BEMF:BEMFRISINGWITHPNSLOPE=1ORBEMFFALLINGWITHPNSLOPE=0
BEMF1:BEMFRISINGWITH PNSLOPE=0ORBEMFFALLING WITHPNSLOPE=1
**MONO=0WHENFREQ(BEMF)=2*FREQ(PHASE)
***MINMASK=192/SYS_CLK(I.E.WITHSYS_CLK=10MHz,MIN MASK=19.2μs)
D95IN280
192/FALIGN
64/FALIGN
OUTENA=0
SYS_CLK
OUTENA=0
OUTENA=1
BEMF
POR=0
FROM ANYSTATE
(FOR ISGENERATEDINTERNALLY
BYMONITORINGVLOGIC)
Figure 2-1
L6238S
10/31
Bemf. This resychronization can either occur
whenever Output Enable or Run/Brakeis first
brought low then high.
Referring to figure 2-4, the ”Hold for Resync”
stateis brought low. The controller leaves this
state and enters ”Start Resync” when Output En-
ableis high.Q START-UP
LOGIC
OVERTEMP SHUTDOWN
D95IN311OUTPUT
ENABLE
RUN/
BRAKE
FALIGN
Figure 2.3: Watch-Dog Timer
LOAD MINDELAY
LOAD MINMASK***
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
LOAD DELAY=MIN
LOAD MASK=MIN
PERIODCOUNT
DELAYCOUNT*
STATE=STATE+1
MASKCOUNT
CHECK FORZc
OUTENA=1
BEMF
DRIVERSOFF
MINCLOCKDELAY
PERIODSTOP
D95IN312
*CLOCKDELAY=(TDLY [2:0]WHENBEMF PERIOD<3.3ms@10MHz(SPEED>12.7HzFOR 8POLES)
BEMF:BEMF RISINGWITHPNSLOPE=1ORBEMFFALLINGWITHPNSLOPE=0
BEMF:BEMF RISINGWITHPNSLOPE=0ORBEMFFALLINGWITHPNSLOPE=1
**MONO=0 WHENFREQ (BEMF)=2*FREQ(PHASE)
***MIN MASK=192/SYS_CLK(I.E.WITHSYS_CLK=10MHz,MIN MASK=19.2μs)
BEMF
RUN/BRK=0
BEMF
BEMF
DRIVERSOFF
DRIVERSON
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIODCOUNT
DELAYH COUNT*
STATE=STATE+1
MASKCOUNT
MONO=0** BEMF
BEMF
RUN
MODE
OUTENA=0
OUTENA=1
HOLD FOR RESYNC
RESYNCHRONIZATION MODE
Figure 2-4
STATE=1
DRIVERSOFF
MINCLOCKDELAY
PERIODSTOP
DELAYSTOP
MASKSTOP
DRIVERSOFF
MINCLOCKDELAY
LOADMINDELAY
LOADMINMASK
PERIODSTOP
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
CHECKFORZc
DRIVERSON
PERIODSTOP
DELAYSTOP
MASKSTOP
STATE=STATE+1
LOADDELAY=MIN
LOADMASK=MAX
PERIODCOUNT
DELAYCOUNT
STATE=STATE+1
MASKCOUNT
CHECKFORZc
BEMF
SYS_CLK
RUN/BRAKE=1
POR=0
FROMANYSTATE
OUTENA=1
64/FALIGN
192/FALIGN
DRIVERSON
LOADDELAY=PERIOD
LOADMASK=PERIOD
RESETPERIOD
PERIODCOUNT
DELAYCOUNT*
STATE=STATE+1
MASKCOUNT
BEMF
D95IN310BEMF:BEMF RISINGWITHPNSLOPE=1ORBEMFFALLINGWITHPNSLOPE=0
BEMF:BEMF RISINGWITHPNSLOPE=0ORBEMFFALLINGWITHPNSLOPE=1
***MINMASK=192/SYS_CLK(I.E. WITHSYS_CLK=10MHz,MINMASK=19.2μs)
BEMF
RUN/BRK=0
FROM ANYSTATE
Figure 2.2
L6238S
11/31
zero crossings are detected, the sequencer willautomatically lockonto the proper phase.
This resynchronization will take effect with the
motor speed runningas low as typically 30%of
it’s nominal value.
2.5 External Sequencing
Although the user-defined Start-Up Algorithmis
flexible and will consistently spinupa motor with external interaction, the possibility exists
where certain applications might require complete
microprocessor controlof start-up.
The L6238S offers this capability via the SE-
QUENCE INCREMENT input. Referringto figure
2-5, during initial power-up with Output Enable
low, the controllerisin the ”Hold and Wait for De-
cision” state.If the SEQUENCE INCREMENT pin brought high during this state, the Auto StartUp
Algorithmis disabled and the sequencer can be
controlledexternally.
When Output Enable and Run/Brake are
brought high, the sequenceris incremented on
each positive transitiono the SEQUENCER IN-
CREMENT pin. During the time that this pinis
high,all Bemf informationis masked out. Whenit low, the Bemf information canbe detected nor-
mally after the internal mask time. The minimum
mask timeis 192/Sys_Clk (i.e. with Sys_Clk=
10MHz, min. mask= 19.2μs) Thereforeto insure
that the sequenceris under complete controlof
the state machine, the time that the SEQUENCE
INCREMENT pinis held low should be much less
then the min. mask time, but greater then 1μs.
When the motor has reacheda predetermined
speed, the SEQUENCE INCREMENT pin can be
left low and the L6238S Motor Control logic will
take over and automatically spin up the motorto
the desiredspeed
3.0 START-UP ALGORITHMS
3.1 Spin-Up Operation
The spinoperation canbe separated into3 parts: Open Loop Start-Up- The objectisto create
motionin the desired directionso that the Bemf
voltagesat the3 motor terminals can provide reli-
able information enablinga transitionto closed
loop operation.
STATE=1
DRIVERSOFF
MIN CLOCKDELAY
PERIOD STOP
DELAYSTOP
MASKSTOP
INT START-UPDISABLED
MIN CLOCKDELAY
LOAD MINDELAY
LOAD MINMASK
MASKCOUNT
SEQINC=1&
OUTENA=0
RUN/BRK=X
D95IN313*VALIDIFSEQINC=0, ANDDELAYTIMESOUT
**CLOCKDELAY=F(TDLY_[2:0])
WHENBEMFPERIOD <3.3ms @10MHz(SPEED>12.7HzFOR 8POLES)
SEQINC=0
STATE=STATE+1
MASKCOUNT
LOAD DELAY=PERIOD
LOAD MASK=PERIOD
RESET PERIOD
PERIOD COUNT
DELAYCOUNT**
BEMF
POR=0
FROM ANYSTATE
DRIVERSON
PERIOD COUNT
DELAYCOUNT
SEQINC=0
BEMF
SEQINC=1
STATE=STATE+1SEQINC=1
FROMANYSTATE
WITH SEQ_INC=0
RETURNTO
PREVIOUS STATE
(CHANGINGSEQINC=1)
RUN/BRK=1&
OUTENA=1
SEQINC=1
Figure 2-5
L6238S
12/31
Closed Loop Start-Up- The Bemf voltagezerocrossings provide timing information so that
the motor can be acceleratedto steady state
speed. Steady-State Operation- The Bemf voltage
zero-crossings provide timing information for pre-
cision speed control.
The L6238S contains features that offer flexible
control over the start-up procedure. Either the on-
board Auto-Start Algorithm canbe usedto control
the start-up sequenceor more sophisticated ex-
tenal start-up algorithms can be developed using
the Serial Port and key control/sense functions
brought outto pins.
3.2 Auto-Start Algorithm
When initially powered up, the controller defaults the internal AutoStart Mode. When Run/Brake low, the L6238Sisin brake mode, and the
Auto-Start Algorithmis reset.In the brake mode,
allof the lower DMOS drivers are ON, and the up-
per drivers are OFF.
The Auto-Start Algorithmis based on an Align& approach and canbe visualizedby referringto
Figure 3-1. Shown are the Run/Brake control sig-
nals, sequencer function, and the three output
voltage waveforms.
Referringto figure 3-1, the followingis the se-
quenceof events during Auto-Start:
With Output Enable =1, Run/Brake =0 State Machineis setto State1 with the drivers
Trisatted.
Alignment Phase (1)
Run/Brake =1 Output Stageis sequencedto State2 and the
drivers energized with OUTPUTA high and
OUTPUTC lowfor 64/Falign seconds.
Alignment Phase(2) Output Stageis double sequencedto State4
with OUTPUTB high and OUTPUTA lowfor
STATE2
A=HIGH
B=FLOAT
C=LOW
STATE4
A=LOW
B=HIGH
C=FLOAT
STATE6
A=FLOAT
B=LOW
C=HIGH
500ms/DIV*FALIGN=90Hz
AOUT10V
BOUT10V
COUT10V
ALIGNMENT GO
DOUBLEINCREMENTS
*0.711s *2.133s
RUN/BRAKE
SEQUENCER
D95IN314
Figure 3-1: Align+Go
L6238S
13/31
192/Falign seconds. During the alignment phase, the SEQ INCRE-
MENT signalis ignored. Phase The internal sequencer double increments the
output stageto State6, which should produce
torquein the desired direction. with SEQ INCREMENT held low, the se-
quenceris now controlledby the Bemf zero
crossings, and the motor should ramp upto
speed.
3.3 Externally Controlled Start-Up Algorithms
Enhanced Start-Up Algorithms can be achieved usinga μProcessor to interact with the
L6238S.’ The L6238S has the abilityto transition Closed Loop Start-Upat very low speeds, re-
ducing the uProcessor taskto monitoring status
rather than real time interaction. Thus,itisa per-
fect applicationforan existing μProcessor.
The following control and status signals allow for
very flexiblealgorithm development:
SEQ_INCRA lowto high transitionat this input usedto increment the stateof the power out-
put stage.Itis useful during start-up, because
the μProcessor can cycleto any desired state, cycle through the statesat any desired rate.
When held high,it inhibits the BEMF zero
crossings from incrementing the internal se-
quencer.
SPIN SENSE This outputis low until the first
detected Bemf zero crossing occurs.It then
togglesat each successive zero crossing. This
signal servesasa motion detector and gives
useful timing informationas well as the slope the Bemf.
3.4 Start Up Approaches
Align& Go Approach The Align& Go approach
providesa very time efficient algorithmby ener-
gizing the coilsto align the rotor and statortoa
known phase. This approach canbe achieved via
the sequencing SEQ INCR. SPIN SENSE canbe
monitoredto assure that motion occurred. Once
ample timeis given for alignmentto occur, SEQ
INCR canbe double incremented, and the SPIN
SENSE pin canbe monitoredto detect motion.
When SEQ INCRis pulled low, controlis trans-
ferredto the internal sequencer, and the L6238S
finishes the spinup operation.If no motionis de-
tected, SEQ INCR canbe incrementedtoa differ-
ent phase and the process can be repeated. The
alignment phase may cause backward rotation,
which on the average will be greater than the
Stepper Motor approach.
The Auto-Start algorithm described earlieris an
Align& Go approach. The main advantagesof
the integrated Auto-Start are that the μPis notin-
volved real-time, and there area minimumof in-
terface pins requiredto the spindle control sys-
tem.
Stepper Motor Approach This approach mini-
mizes backward rotation by sequencing SEQ
INCRat an initial rate that the rotor can follow.
Thus,itis drivenina similar fashiontoa stepper
motor. The rateis continually increased until the
Bemf voltageis large enoughto reliably use the
zero-crossings for commutation timing. SEQ
INCRis held low, causing controltobe passedto
the L6238S’sinternal sequencerasin the Align& approach.
The Stepper Motor approach takes longer than
the Align& Go approach because the initial com-
mutation frequency and subsequent ramp rate
must be low enoughso that the motor can follow
without slipping. This implies thatto havea reli-
able algorithm, the initial frequency and ramp rate
must be chosen for the worst case motor under
worst case conditions.
4.0 MOTOR DRIVER
4.1 Output Stage
The output stage formsa 3-Phasefull wave bridge
consistingof six Power DMOS FET High output
currents are allowed for bbrief periods. High out-
put currents are allowed for brief periods. Output
Power exceeding the stand-alone power dissipa-
tion capabilitiesof the L6238S canbe increased
with the additionof an external P-FETorby the
useof Pulse-Width-Modulation.
Table 4-1isa reference diagram that lists the pa-
rameters associated with 8-pole motors operating 3600 and 5400 RPM.
Figure 4-1 represents the waveforms associated
with the output stage. The upper portionof figure
4-1 shows the flowof currentin the motor wind-
ings for eachof the24 phase increments.A rota-
tional degree indexis shownasa referencealong
witha base lineto indicate the occurrenceofa
zero crosing.The output waveforms area digitally
reproduced voltage signalsas measuredon sam-
ples.The feedback Inputis multiplexed between
the internal Bemf Zero Crossing Detector and an
externally provided sync pulse (EXT INDEX)
Shownin figure10is the classical state diagram
fora phase detector along with waveform exam-
ples. typical sequence starts when the outputs
switch states. Referring to figure 4-1, during
phase1, outputA goes high, while outputBis low.
During this phase, outputCis floating, and the
Bemfis monitored. The outputs remainin this
statefor 60 electrical degreesas indicatedby the
first setof dashed lines. After this period the out-
L6238S
14/31
Table 4-1
Rotational Speed 3600rpm 5400rpm
Rotational Frequency 60Hz 90Hz
Rotational Period 16.667ms 11.111ms
Electrical Period 4.167ms 2.778ms
Phase Period 694.5μs 463.0
Figure 4-1: Waveforms
L6238S
15/31
put switchedto phase2 with outputA high andC
low with the Bemf amplifier monitoring outputB. orderto prevent commutation current noise be-
ing detectedmasa false zero crossing,a mask-
ing circuit automatically blanks out all incoming
signals as soon asa zero crossingis detected.
When the next commutation occurs an internal
counter starts counting downto set the time that
the masking pulse remains.
The counteris initially loaded witha number that equalto time thatis always 25%of the previous
phase periodor 15 electrical degrees. The time-
outof the masking pulse shown for referenceat
the bottomof figure 4-1. Thus the actual masking
periodis the totalof the time from the detected
zero crossingto the phase commutation, plus
25%of the previous period. The mask pulse op-
erationis further discussedin section 4.6, Slew
Rate Control and PWM operation.
After the masking period, the Bemf voltageat out-
putBis monitored fora zero crossing. Upon de-
tectionof the crossing, the outputis commutated
after the selected phase delay insuring maximum
torque. The spin sense waveformat the bottomof
the figure indicates that this output signal toggles
with each zero crossing.
4.2 BrakeDelay
When Run/Brakeis brought low,a brakeis initi-
ated. Referringto figure 4-2, SW1is opened and
the brake delay capacitor, Cbrake,is allowedto
discharge towards groun via Rbrake. the same time, switches SW2 through SW7
bring the gatesof the output FETsto ground halt-
ing conduction, causing the motorto coast. While
the motoris coasting, the Bemfis usedto park
the heads. When Cbrake reachesa voltage that below the turn ON thresholdof Q1, Switches
SW8,9, and 10 bring the gatesof the lower driv-
ersto Vbrake potential. This enables the lower
FETs causinga braking action.
The analog and logic supplies are not monitored the L6238S, since the L6244 already monitors
this voltage and initiatesa Park function when
either supply dropstoa predeterminated level.
Figure 4-2
L6238S
16/31

Partno	Mfg	Dc	Qty	Available	Descript
L6238S	ST	N/a	2500	avai	12V SENSORLESS SPINDLE MOTOR CONTROLLER
L6238SQA		N/a	63	avai	12V SENSORLESS SPINDLE MOTOR CONTROLLER
L6238SQT	ST	N/a	4000	avai	12V SENSORLESS SPINDLE MOTOR CONTROLLER