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L6227Q-L6227QTR
PowerSPIN: DMOS dual full bridge driver with PWM current controller
January 2009 Rev 3 1/27
L6227QDMOS dual full bridge driver
with PWM current controller
Features Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A DC) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Operating frequency up to 100 kHz Non dissipative overcurrent protection Dual independent constant tOFF PWM current
controllers Slow decay synchronous rectification Cross conduction protection Thermal shutdown Under voltage lockout Integrated fast free wheeling diodes
Applications Bipolar stepper motor Dual or quad DC motor
DescriptionThe L6227Q is a DMOS dual full bridge designed
for motor control applications, realized in
BCDmultipower technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. The device also
includes two independent constant off time PWM
current controllers that performs the chopping
regulation. Available in VQFPN32 5 mm x 5 mm
package, the L6227Q features a non-dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.
Figure 1. Block diagram
Contents L6227Q
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Contents Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 T ruth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output current capability and IC power dissipation . . . . . . . . . . . . . . 21 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L6227Q Electrical data
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1 Electrical data
1.1 Absolute maximum ratings
1.2 Recommended operating conditions
Table 1. Absolute maximum ratings
Table 2. Recommended operating conditions
Electrical data L6227Q
4/27
1.3 Thermal data
Table 3. Thermal data Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 2 ground layer connected through 18 via holes (9 below the IC).
L6227Q Pin connection
5/27
2 Pin connection
Figure 2. Pin connection (top view)
Note: 1 The pins 2 to 8 are connected to die PAD The die PAD must be connected to GND pin
Pin connection L6227Q
6/27
Table 4. Pin description Also connected at the output drain of the over current and thermal protection MOSFET. Therefore, it has to be driven
putting in series a resistor with a value in the range of 2.2 kΩ - 180 kΩ, recommended 100 kΩ.
L6227Q Electrical characteristics
7/27
3 Electrical characteristics
Table 5. Electrical characteristics (TA = 25 °C, Vs = 48 V, unless otherwise specified)
Electrical characteristics L6227Q
8/27 Tested at 25 °C in a restricted range and guaranteed by characterization. See Figure 3 on page9 Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. See Figure 4 on page9
Table 5. Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)
L6227Q Electrical characteristics
9/27
Figure 3. Switching characteristic definition
Figure 4. Overcurrent detection timing definition
Circuit description L6227Q
10/27
4 Circuit description
4.1 Power stages and charge pump
The L6227Q integrates two independent power MOS Full Bridges. Each power MOS has an
RDS(on) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross
conduction protection is achieved using a dead time (td = 1 µs typical) between the switch
off and switch on of two power MOS in one leg of a bridge.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table6.
Figure 5. Charge pump circuit
Table 6. Charge pump external components values
L6227Q Circuit description
11/27
4.2 Logic inputs
Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS and microcontroller compatible logic inputs.
The internal structure is shown in Figure 6. Typical value for turn-on and turn-off thresholds
are respectively Vthon = 1.8 V and Vthoff = 1.3 V.
Pins ENA and ENB have identical input structure with the exception that the drains of the
Overcurrent and thermal protection MOSFETs (one for the bridge A and one for the
bridge B) are also connected to these pins. Due to these connections some care needs to
be taken in driving these pins. The ENA and ENB inputs may be driven in one of two
configurations as shown in Figure 7 or Figure 8. If driven by an open drain (collector)
structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 7. If
the driver is a standard push-pull structure the resistor REN and the capacitor CEN are
connected as shown in Figure 8. The resistor REN should be chosen in the range from
2.2 kΩ to 180 kΩ . Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF.
More information on selecting the values is found in the overcurrent protection section.
Figure 6. Logic inputs internal structure
Figure 7. EN and EN pins open collector driving
Figure 8. ENA and ENB pins push-pull driving
Circuit description L6227Q
12/27
4.3 Truth table
4.4 PWM current control
The L6227Q includes a constant off time PWM current controller for each of the two bridges.
The current control circuit senses the bridge current by sensing the voltage drop across an
external sense resistor connected between the source of the two lower power MOS
transistors and ground, as shown in Figure 9. As the current in the load builds up the voltage
across the sense resistor increases proportionally. When the voltage drop across the sense
resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the
sense comparator triggers the monostable switching the low-side MOS off. The low-side
MOS remain off for the time set by the monostable and the motor current recirculates in the
upper path. When the monostable times out the bridge will again turn on. Since the internal
dead time, used to prevent cross conduction in the bridge, delays the turn on of the power
MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 9. PWM current controller simplified schematic
Table 7. Truth table Valid only in case of load connected between OUT1 and OUT2 X = don't care High Z = high impedance output GND (Vs) = GND during Ton, Vs during Toff
L6227Q Circuit description
13/27
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately
after the low-side power MOS turns on, a high peak current flows through the sensing
resistor due to the reverse recovery of the freewheeling diodes. The L6227Q provides a 1 µs
blanking time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
Figure 10. Output current regulation waveforms
Figure 11 shows the magnitude of the off time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
Dead Time with:
20 kΩ ≤ ROFF ≤ 100 kΩ
0.47 nF ≤ COFF ≤ 100 nF
tDT = 1 µs (typical value)
Therefore:
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms
Circuit description L6227Q
14/27
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the rise time tRCRISE of the voltage at the
pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a
good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller
than the minimum on time tON(MIN). RCRISE = 600 · C OFF
Figure 12 on page 15 shows the lower limit for the on time tON for having a good PWM
current regulation capacity. It has to be said that tON is always bigger than t ON(MIN) because
the device imposes this condition, but it can be smaller than t RCRISE - tDT . In this last case
the device continues to work but the off time t OFF is not more constant.
So, small C OFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but, the smaller is the value for C OFF , the more
influential will be the noises on the circuit performance.
Figure 11.t OFF versus C OFF and R OFFONtON MIN()> 2.5µs=ONt TCRISEtDT–>⎩⎨⎧
