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L6123STN/a100avai100 V DMOS SWITCHES
L6123ST ?N/a51avai100 V DMOS SWITCHES


L6123 ,100 V DMOS SWITCHESapplications. Each of thethree switches is controlled by a logic input and allthree are controlled ..
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L6123
100 V DMOS SWITCHES
L6122 6123
April 1993
100 V DMOS SWITCHES
ADVANCE DATA
. OUTPUT VOLTAGE TO 100V. 0,5Ω RDS (on). SUPPLY VOLTAGE UP TO 60V. LOW INPUT CURRENT. TTL/CMOS COMPATIBLE INPUTS. HIGH SWITCHING FREQUENCY (200kHz)
DESCRIPTION

Realized with the Multipower-BCD mixed bipo-
lar/CMOS/DMOS process, the L6122/23 monolithic
three DMOS switch is designed for high current,
high voltage switching applications. Each of the
three switches is controlled by a logic input and all
three are controlled by a common enable input. All
inputs are TTL/CMOS compatible for direct connec-
tion to logic circuits. Each source is available for the
insertion of the sense resistors in current control ap-
plications.
Two versions are available : the L6122 mounted in
a Powerdip 14 + 3 + 3 package and the L6123 in a
15-lead Multiwatt package.
1/9
PIN CONNECTIONS (top view)
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS

(*) Pulse width ≤ 300 μs, duty cycle ≤ 10 %.
NOTE : ID, IDM, ISD, ISDM are given per channel.
THERMAL DATA
L6122 - L6123

2/9
SWITCHING TIMES RESISTIVE LOAD
Figure 1 : Test Circuit.
ELECTRICAL CHARACTERISTICS (Tj = 25
o C, VCC = 40V, unless otherwise specified)
(*) Pulse test : pulse width = 300 μs, duty cycle = 2 %.
L6122 - L6123

3/9
Figure 2 : Waveforms.
Figure 3 : Static Drain-source on Resistance. Figure 4 : Normalized Breakdown Voltage vs.

Temperature.
Figure 5 : Normalized on Resistance vs. Tempe-

rature.
Figure 6 : Typical Source-drain Diode Forward

Voltage.
L6122 - L6123

4/9
Figure 7 : Rth j-amb vs. Dissipated Power (Multiwatt).
(*) Rth ≈ 9°C/W
Figure 8 : Transient Thermal Resistance for Single Pulses (Multiwatt).
L6122 - L6123

5/9
Figure 9 : Peak Transient Thermal Resistance vs. Pulse Width and Duty Cycle (Multiwatt).
L6122 - L6123

6/9
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