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IRS2127IRN/a11avai600V Current Sensing Single Channel Driver with Gate Drive Range of 12V
IRS2127SPBFIRN/a12avai600V Current Sensing Single Channel Driver with Gate Drive Range of 12V
IRS2128IRN/a528avai600V Current Sensing Single Channel Driver with Gate Drive Range of 12V


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IRS2127-IRS2127SPBF-IRS2128
600V Current Sensing Single Channel Driver with Gate Drive Range of 12V
International
19R Rectifier
Data Sheet No. PD60299
IRS212(7, 71, 8, 81)(S)PbF
CURRENT SENSING SINGLE CHANNEL DRIVER
Featu res
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage dV/dt immune
Application-specific gate drive range:
Motor Drive: 12 V to 20 V (lRS2127/lRS2128)
Automotive: 9 V to 20 V (lRS21271/lRS21281)
Undervoltage lockout
3.3 V, 5 V, and 15 V input logic compatible
FAULT lead indicates shutdown has occured
Output in phase with input (lRS2127/lRS21271)
Output out of phase with input (lRS2128/lRS21281)
RoHS compliant
Description
The lRS2127/lRS2128/lRS21271/lRS21281 are
high voltage, high speed power MOSFET and IGBT
drivers. Proprietary HVIC and latch immune CMOS
technologies enable ruggedized monolithic construc-
tion. The logic input is compatible with standard
CMOS or LSTTL outputs, down to 3.3 V. The protec-
tion circuity detects over-current in the driven power
transistor and terminates the gate drive voltage. An
open drain FAULT signal is provided to indicate that
an over-current shutdown has occurred. The output
Product Summary
VOFFSET 600 V max.
lo+l- 200 mA I 420 mA
VOUT 12V-20V 9V-20V
(lRS2127llR2128) (lRS21271llR21281)
VCSth 250 mV or 1.8 V
tonloff(typ.) 150 ns & 150 ns
Packages
8-Lead PDIP 8-Lead SOIC
driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating chan-
nel can be used to drive an N-channel power MOSFET or IGBT in the high-side or Iow-side configuration which
operates up to 600 V.
Typical Connection
circuit board layout.
vm C __ V CD V B __ , '
N c " IN HO A
We FAULT CS
COM v S o I
= >. o
--- IRS2127llRS21271 vmc - VCC VB __ F,
N c f“ N HO [w
m o FAULT CS
(Refer to Lead Assignments for correct pin configuration). COM V 0
These diagrams show electrical connections only. Please s
refer to our Application Notes and DesignTips for proper IRS2128llRS21281


International IRS212(7, 71, 8, 81)(S)PbF
TOR Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VB High-side floating supply voltage -0.3 625
vs High-side floating offset voltage VB - 25 " + 0.3
VH0 High-side floating output voltage vs - 0.3 VB + 0.3
Vcc Logic supply voltage -0.3 25 V
VlN Logic input voltage -O.3 VCC + 0.3
VFLT TULT output voltage -0.3 Vcc + 0.3
Vcs Current sense voltage Vs - 0.3 VB + 0.3
st/dt Allowable offset supply voltage transient - 50 V/ns
PD Package power dissipation © TA 5 +25 ''C 81ead DIP - 1.0 W
8-Lead SOIC - 0.625
RthJA Thermal resistance, junction to ambient 81ead DIP - 125 "C/W
8-lead SOIC - 200
TJ Junction temperature - 150
Ts Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. l. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at 15 V differential.
Symbol Definition Min. Max. Units
. . . (lRS2127/lRS2128) vs + 12 vs + 20
VB High-side floating supply voltage
(lRS21271/lRS21281) Vs + 9 Vs + 20
Vs High-side floating offset voltage Note 1 600
VH0 High-side floating output voltage vs VB
Vcc Logic supply voltage 10 20 V
VlN Logic input voltage 0 ve
VFLT WT output voltage 0 Vcc
I/cs Current sense signal voltage vs vs + 5
TA Ambient temperature -40 125 ''C
Note 1: Logic operational for vs of -5 V to +600 V. Logic state held for Vs of E V to IBS. (Please refer to the Design Tip
DT97-3 for more details).
2

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