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IRS2003-IRS2003SPBF
Half Bridge Driver, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels
Data Sheet No. PD60269
International
B2R Rectifier IRS2003(S)PbF
HALF-BRIDGE DRIVER
Features
Product Summa
q Floating channel designed for bootstrap operation ry
0 Fully operational to +200 V VOFFSET 200 V max.
0 Tolerant to negative transient voltage, dV/dt
immune kyr/- 130 mA/270 mA
0 Gate drive supply range from 10 V to 20 V
0 Undervoltage lockout VOUT 10 V - 20 V
0 3.3 V, 5 V, and 15 V logic compatible
0 Cross-conduction prevention logic ton/off (typ.) 680 ns/150 ns
0 Matched propagation delay for both channels .
0 Internal set deadtime Deadtime (typ.) 520 ns
0 High-side output in phase with HIhCinput
. Low-side output out of phase with LIN input Packages
0 RoHS compliant
Description ofitiiti,is
The IRS2003 is a high voltage, high speed power 'ct/ii'''''
MOSFET and IGBT drivers with dependent high- and
low-side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rugge- 8-Lead PDIP 8-Lead soc
dized monolithic construction. The logic input is IRS2003 IRS2003S
compatible with standard CMOS or LSTTL output, down
to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates up to 200 V.
Typical Connection
up to Loo V
Vcc C V]
Er F-T
-- Vcc VB __
KN r-x
HIN o H I N HO
W o LIN V 0 TO
S LOAD
COM LO _
(Referto Lead Assignments for correct conhguration). This diagram shows electrical connections only. Please refer to
ourApplication Notes and DesignTips for proper circuit board layout.
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International IRS2003(S)PbF
TOR Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VB High-side floating absolute voltage -0.3 225
Vs High-side floating supply offset voltage VB - 25 VB + 0.3
VH0 High-side floating output voltage Vs - 0.3 VB + 0.3 V
Vcc Low-side and logic fixed supply voltage -O.3 25
VLo Low-side output voltage -0.3 Vcc + 0.3
VIN Logic input voltage (HIN & W) -0.3 VCC + 0.3
dl/s/dt Allowable offset supply voltage transient - 50 V/ns
. . . (8 Lead PDIP) - 1.0
PD Package power dissipation @ TA 3 +25 °C W
(8 Lead SOIC) - 0.625
. . . . (8 Lead PDIP) - 125
RthJA Thermal resistance, junction to ambient °C/W
(8 Lead SOIC) - 200
TJ Junction temperature - 150
Ts Storage temperature -55 150 ''C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 Vs + 20
VS High-side floating supply offset voltage Note 1 200
VH0 High-side floating output voltage Vs VB
Vcc Low-side and logic fixed supply voltage 10 20 V
VLo Low-side output voltage 0 Vcc
VIN Logic input voltage (HIN & W) 0 Vcc
TA Ambient temperature -40 125 °C
Note 1: Logic operational for Vs of -5 V to +200 V. Logic state held for Vs of -5 V to A/BS. (Please refer to the Design Tip
DT97-3 for more details).
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