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IR21844PBF-IR2184PBF
Half Bridge Driver
Data Sheet No. PD60174 revG
International
IéaR Rectifier IR2184(4)(S)&(PbF)
HALF-BRIDGE DRIVER
Features
q Floating channel designed for bootstrap operation P ackages
Fully operational to +600V
Tolerant to negative transient voltage ~
dV/dt immune 'iii', 14-Lead PDIP
q Gate drive supply range from 10 to 20V ‘ IR21844
q Undervoltage lockout for both channels 8-Lead PDIP
q 3.3V and 5V input logic compatible IR2184
o Matched propagation delay for both channels
q Logic and power ground +/- 5V offset.
q Lower di/dt gate driver for better noise immunity Lu
q Output source/sink current capability 1.4A/1.8A 8-Lead SOIC
. 14-Lead SOIC
q Also available LEAD-FREE (PbF) IR2184S IR21844S
Description
IR2181llR2183llR2184 Feature Com arison
The IR2184(4)(S) are high voltage, C p
high speed power MOSFET and IGBT I t 2'gr, . .
drivers with dependent high and low Part i222 gfgvejrftilgrr: Dead-Time Ground Pins Ton/Toff
side referenced output channels. Pro- 2181 logic COM
prietary HVIC and latch immune 21814 HIN/LIN no none VSS/COM 180/220ns
CMOS technologies enable rugge- 2183 HIN/LTN Internal500ns COM 1801220
dized monolithic construction. The 2211883: yes "ereag1, ht; 5 us ”§§th ns
logic input is compatible with standard 21844 WISE yes Frog“ JESUS VSS,COM 680/270 ns
CMOS or LSTTL output, down to 3.3V
logic. The output drivers feature a
high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be
used to drive an N-channel power MOSFET or IGBT in the high side conhguration which operates up to 600
volts.
Typical Connection
up to 600V
IR2184
IR21844
(Refer to Lead Assignments for correct
configuration). This/These diagram(s) show Vss
electrical connections only. Please refer to
our Application Notes and DesignTips for
proper circuit board layout.
IR2184(4)(S)&(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
International
TDR Rectifier
Symbol Definition Min. Max. Units
VB High side floating absolute voltage -0.3 625
Vs High side floating supply offset voltage VB - 25 Vs + 0.3
VH0 High side floating output voltage Vs - 0.3 V3 + 0.3
Vcc Low side and logic fixed supply voltage -O.3 25 V
VLo Low side output voltage -O.3 Vcc + 0.3
DT Programmable dead-time pin voltage (IR21844 only) VSS - 0.3 VCC + 0.3
VIN Logic input voltage (IN & s7) Vss - 0.3 Vss + 10
I/ss Logic ground (IR21844 only) VCC - 25 Vcc + 0.3
st/dt Allowable offset supply voltage transient - 50 V/ns
PD Package power dissipation @ TA s: +25°C (8-Iead PDIP) - 1.0
(8-lead SOIC) - 0.625
(14-lead PDIP) - 1.6 W
(14-Iead SOIC) - 1.0
RthJA Thermal resistance, junction to ambient (8-lead PDIP) - 125
(8-Iead SOIC) - 200
(14-Iead PDIP) - 75 oC/W
(14-Iead SOIC) - 120
TJ Junction temperature - 150
Ts Storage temperature -50 150 "C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The Vs and vss offset rating are tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
VB High side Mating supply absolute voltage VS + 10 Vs + 20
VS High side floating supply offset voltage Note 1 600
VH0 High side floating output voltage Vs Vs
Vcc Low side and logic fixed supply voltage 10 20
VLO Low side output voltage 0 Vcc V
VIN Logic input voltage (IN & STO) vss l/ss + 5
DT Programmable dead-time pin voltage (IR21844 only) vss Vcc
Vss Logic ground (IR21844 only) -5 5
TA Ambient temperature -40 125 ''C
Note 1: Logic operational for Vs of -5 to +6OOV. Logic state held for vs of -5V to NBS. (Please refer to the Design Tip
DT97-3 for more-details).
Note 2: IN and SD are internally clamped with a 5.2V zener diode.
