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IR2125N/a18avaiSingle High Side Driver, Current Limiting, Programmable Shutdown Error Pin in a 8-pin DIP package
IR2125SIRN/a2157avaiSingle High Side Driver, Current Limiting, Programmable Shutdown Error Pin in a 16-lead SOIC package


IR2125S ,Single High Side Driver, Current Limiting, Programmable Shutdown Error Pin in a 16-lead SOIC packageFeaturesProduct Summary• Floating channel designed for bootstrap operationV 500V max.OFFSETFully op ..
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IR2125-IR2125S
Single High Side Driver, Current Limiting, Programmable Shutdown Error Pin in a 8-pin DIP package
features a high pulse current(Wide Body)buffer stage designed for minimum driver cross-conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive volt-age. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time intervalbetween detection of the over-current limiting conditions and latched shutdown. The floating channel can be used todrive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 500 volts.Typical Connectionup to 500VVV VCCCC BININ HOERR CSTOCOM VSLOAD(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electricalconnections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. 1( )IR2125 SAbsolute Maximum RatingsAbsolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measuredunder board mounted and still air conditions.Symbol Definition Min. Max. UnitsV High Side Floating Supply Voltage -0.3 525BV High Side Floating Offset Voltage V - 25 V + 0.3S B BV High Side Floating Output Voltage V - 0.3 V + 0.3HO S BV Logic Supply Voltage -0.3 25 VCCV Logic Input Voltage -0.3 V + 0.3IN CCV Error Signal Voltage -0.3 V + 0.3ERR CCV Current Sense Voltage V - 0.3 V + 0.3CS S BdV /dt Allowable Offset Supply Voltage Transient — 50 V/nssP Package Power Dissipation @ T ≤ +25°C (8 lead PDIP) — 1.0D AW (16 lead SOIC) — 1.25Rth Thermal Resistance, Junction to Ambient (8 lead PDIP) — 125JA°C/W (16lLead SOIC) — 100T Junction Temperature — 150JT Storage Temperature -55 150 °CST Lead Temperature (Soldering, 10 seconds) — 300LRecommended Operating ConditionsThe Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within therecommended conditions. The V offset rating is tested with all supplies biased at 15V differential.SSymbol Definition Min. Max. UnitsV High Side Floating Supply Voltage V + 12 V + 18B S SV High Side Floating Offset Voltage Note 1 500SV High Side Floating Output Voltage V VHO S BV Logic Supply Voltage 0 18 VCCV Logic Input Voltage 0 VIN CCV Error Signal Voltage 0 VERR CCV Current Sense Signal Voltage V VCS S BT Ambient Temperature -40 125 °CANote 1: Logic operational for V of -5 to +500V. Logic state held for V of -5V to -V . (Please refer to the Design TipS S BSDT97-3 for more details).2 ( )SIR2125Dynamic
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