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IPD03N03LAInfineonN/a25200avaiOptiMOS®2


IPD03N03LA ,OptiMOS®2characteristicsDrain-source breakdown voltage V V =0 V, I =1 mA 25 - - V(BR)DSS GS DV V =V , I =70 ..
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IPD03N03LA
OptiMOS®2
Infineon
technologies
IPD03N03LA G |PSO3N03LA G
optiMOsf2 Power-Transistor F6614,
Product Summary Prod u ct
Features Vos 25 V
. Ideal for high-frequency dc/dc converters RDS(on),max (SMD Version) 3.2 m9.
. Qualified according to JEDECI) for target applications
h, 90 A
. N-channel, logic level
. Excellent gate charge x RDswn) product (FOM) SE“;
. Superior thermal resistance gate
. 175 ''C operating temperature
source
. Pb-free lead plating; RoHS compliant pin 3
Type |PD03N03LA G |PSO3N03LA G
1:35;“
Package P-T0252-3-11 P-T0251-3-11
Ordering Code Q67042-S4249 Q67042-S4253
Marking 03N03LA 03N03LA
Maximum ratings, at Tj=25 ''C, unless otherwise specified
Parameter Symbol Conditions Value Unit
Continuous drain current In Tc=25 002) 90 A
Tc=100 "C 90
Pulsed drain current ho,ruse Tc=25 oc3) 360
Avalanche energy, single pulse EAS ID=90 A, Rss--25 Q 300 mJ
[0:90 A, Vos=20 V,
Reverse diode dv/dt dv/dt dildt=200 Alps, 6 kV/ps
Tj,max=175 ''C
Gate source voltage'') Vss :20 V
Power dissipation Ptot Tc=25 ''C 115 w
Operating and storage temperature Tj, Tstg -55 ... 175 "C
IEC climatic category; DIN IEC 68-1 55/175/56
Rev. 0.93 - target data sheet page 1 2004-10-27
Infineon
'echnologies IPD03N03LA G |PSO3N03LA G
Parameter Symbol Conditions Values Unit
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case RM; - - 1.3 K/W
SMD version, device on PCB RNA minimal footprint - - 75
6 cm2 cooling areas) - - 50
Electrical characteristics, at Tj=25 ''C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage V(BRmss VGS=O V, ID=1 mA 25 - - V
Gate threshold voltage Vegan) VDS=VGSI lr-TO pA 1.2 1.6 2
Z t It d . t I VDS=25 V, Vss=0 V, 0 1 1 A
ero ga e vo age raIn curren DSS Tj=25 ''C - . p
VDS=25 V, Vss=0 V,
Tj=125 ''C - 10 100
Gate-source leakage current less VGS=20 V, VDS=O V - 10 100 nA
Drain-source on-state resistance Roswn) VGS=4.5 V, ID=60 A - 4.3 5.3 mn
VGS=4'5 V, ID=6O A,
SMD version - 4.1 5.1
VGS=1O V, ID=60 A - 2.9 3.4
VGS=10 V, ID=60 A,
SMD version - 2.7 3.2
Gate resistance RG - 1.3 - f2
V >2 l R ,
Transconductance gfs I PSI I DI DS(on)max 56 113 - S
Jo=60 A
I) J-STD20 and JESD22
I) Current is limited by bondwire; with aanJc=1.3 K/W the chip is able to carry 142 A.
3) See figure 3
4) Trmax=150 ''C and duty cycle D <0.25 for Vss<-5 v
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 on (one layer, 70 pm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 0.93 - target data sheet
page 2
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