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IP82C59A from INTERSIL, Intersil 200pcs , DIP,CMOS Priority Interrupt Controller
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IP82C59A INTERSIL N/a 200

Features Description• 12.5MHz, 8MHz and 5MHz Versions Available The Intersil 82C59A is a high performance CMOS PriorityInterrupt Controller manufactured using an advanced 2μm- 12.5MHz Operation. . . . . . . . . . . . . . . . . . . 82C59A-12CMOS process. The 82C59A is designed to relieve the sys-- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59Atem CPU from the task of polling in a multilevel- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5prioritysystem. The high speed and industry standardconfiguration of the 82C59A make it compatible with micro-• High Speed, “No Wait-State” Operation with 12.5MHzprocessors such as 80C286, 80286, 80C86/88, 8086/88,80C286 and 8MHz 80C86/888080/85 and NSC800.• Pin Compatible with NMOS 8259AThe 82C59A can handle up to eight vectored priority inter-• 80C86/88/286 and 8080/85/86/88/286 Compatiblerupting sources and is cascadable to 64 without additionalcircuitry. Individual interrupting sources can be masked or• Eight-Level Priority Controller, Expandable toprioritized to allow custom system configuration. Two modes64 Levelsof operation make the 82C59A compatible with both 8080/85• Programmable Interrupt Modesand 80C86/88/286 formats.• Individual Request Mask CapabilityStatic CMOS circuit design ensures low operating power.The Intersil advanced CMOS process results in performance• Fully Static Designequal to or greater than existing equivalent products at a• Fully TTL Compatiblefraction of the power.• Low Power Operation- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10μA Maximum- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum• Single 5V Power Supply• Operating Temperature Rangeso oC to +70 C- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0o o- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 Co o- M82C59A . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 COrdering InformationPART NUMBERTEMPERATURE5MHz 8MHz 12.5MHz PACKAGE RANGE PKG. NO.o oCP82C59A-5 CP82C59A CP82C59A-12 28 Ld PDIP 0 C to +70 C E28.6o oIP82C59A-5 IP82C59A IP82C59A-12 -40 C to +85 C E28.6o oCS82C59A-5 CS82C59A CS82C59A-12 28 Ld PLCC 0 C to +70 C N28.45o oIS82C59A-5 IS82C59A IS82C59A-12 -40 C to +85 C N28.45o oCD82C59A-5 CD82C59A CD82C59A-12 CERDIP 0 C to +70 C F28.6o oID82C59A-5 ID82C59A ID82C59A-12 -40 C to +85 C F28.6o oMD82C59A-5/B MD82C59A/B MD82C59A-12/B -55 C to +125 C F28.65962-8501601YA 5962-8501602YA - SMD# F28.6o oMR82C59A-5/B MR82C59A/B MR82C59A-12/B 28 Pad CLCC -55 C to +125 C J28.A5962-85016013A 5962-85016023A - SMD# J28.Ao oCM82C59A-5 CM82C59A CM82C59A-12 28 Ld SOIC 0 C to +70 C M28.3 Handling Procedures.File Number 2784.2http:// or 407-727-9207 | Copyright © 19994-182C59APinouts82C59A (PDIP, CERDIP, SOIC) 82C59A (PLCC, CLCC)TOP VIEW TOP VIEW1 28CS VCC2 27 A0WR4 3 2 1 28 27 263 26 INTARD25D6 5 IR74 25 IR7D76 24D5 IR624 IR6D6 5D4 23 IR576 23D5 IR5D3 8 22 IR47 22 IR4D48 21 IR3 21 IR3D3 D2 99 20D2 IR2D110 20 IR210 19 IR1D1D011 19 IR11811 IR0D012 13 14 15 16 17 1812 17 INTCAS 013 16 SP/ENCAS 114 15GND CAS 2PIN DESCRIPTIOND7 - D0 Data Bus (Bidirectional)RD Read InputWR Write InputA0 Command Select AddressCS Chip SelectCAS 2 - CAS 0 Cascade LinesSP/EN Slave Program Input EnableINT Interrupt OutputINTA Interrupt Acknowledge InputIR0 - IR7 Interrupt Request InputsFunctional DiagramINTA INTDATAD -D7 0 BUSCONTROL LOGICBUFFERIR0RDREAD/IR1WRWRITEIN - INTERRUPT IR2LOGICSERVICE PRIORITY REQUEST IR3A0REG RESOLVER REG IR4(ISR) (IRR) IR5CSIR6IR7CAS 0 CASCADEINTERRUPT MASK REGCAS 1 BUFFER(IMR)CAS 2 COMPARATORSP/ENINTERNAL BUSFIGURE 1.4-2D7CAS 0RDCAS 1WRGNDCSCAS 2SP/ EN VCCINT A0INTAIR082C59APin DescriptionPINSYMBOL NUMBER TYPE DESCRIPTIONV 28 I V : The +5V power supply pin. A 0.1μF capacitor between pins 28 and 14 is recommended forCC CCdecoupling.GND 14 I GROUNDCS 1 I CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the82C59A. INTA functions are independent of CS.WR 2 I WRITE: A low on this pin when CS is low enables the 82C59A to accept command words fromthe CPU.RD 3 I READ: A low on this pin when CS is low enables the 82C59A to release status onto the data busfor the CPU.D7 - D0 4 - 11 I/O BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred viathis bus.CAS0 - CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A struc-ture. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode itcan be used as an output to control buffer transceivers (EN). When not in the Buffered Mode it isused as an input to designate a master (SP = 1) or slave (SP = 0).INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to inter-rupt the CPU, thus, it is connected to the CPU's interrupt pin.IR0 - IR7 18 - 25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising anIR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or justby a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implementedon IR0 - 7.INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto thedata bus by a sequence of interrupt acknowledge pulses issued by the CPU.A0 27 I ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).
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