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IP4777CZ38
DVI and HDMI interface ESD protection, DDC buffering, hot plug control and backdrive protection
General descriptionThe IP4777CZ38 is designed for HDMI transmitter host interface protection. The
IP4777CZ38 includes DDC buffering and decoupling, hot plug detect, backdrive
protection, CEC slew rate control, and high-level ESD protection diodes for the TMDS
lines.
The DDC lines use a new buffering concept which decouples the internal capacitive load
from the external capacitive load. This allows greater design flexibility of the DDC lines
with respect to the maximum load of 50 pF specified in the HDMI 1.3 specification. This
buffering also boosts the DDC signals, allowing the use of longer HDMI cables having a
higher capacitive load than 700 pF. The CEC slew rate limiter prevents ringingon the CEC
line. The internal hot plug detect module simplifies the applicationof the HDMI transmitter
to control the hot plug signal.
The DDC, hot plug and CEC lines are backdrive protected to guarantee HDMI interface
signals are not pulled down if the system is powered down or enters standby mode.
All TMDS intra-pairs are protected by a special diode configuration offering a low line
capacitance of 0.7 pF only (to ground) and 0.05 pF between the TMDS pairs. These
diodes provide protection to components downstream from ESD voltages of up to ±8kV
contact in accordance with the IEC 61000-4-2, level 4 standard.
Features HDMI 1.3 compliant Pb-free and RoHS compliant; Dark Green Robust ESD protection without degradation after several ESD strikes Low leakage even after several hundred ESD discharges Very high diode switching speed (ns) and low line capacitanceof 0.7pFto ground and
0.05 pF between channel can ensure signal integrity DDC capacitive decoupling between system side and HDMI connector side and
buffering to drive cable with high capacitive load (> 700 pF) Hot plug detect module CEC ringing prevention by slew rate limiter All TMDS lines with integrated rail-to-rail clamping diodes with downstream ESD
protection of±8 kV in accordance with IEC 61000-4-2, level 4 standard Matched 0.5 mm trace spacing
IP4777CZ38
DVI and HDMI interface ESD protection, DDC buffering,
hot plug control and backdrive protection
Rev. 02 — 12 February 2009 Product data sheet
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection Highest integration in a small footprint, PCB-level, optimized RF routing, 38-pin
TSSOP lead-free package
Applications The IP4777CZ38 can be used for a wide range of HDMI source devices, consumer
and computing electronics e.g.: SD and HD DVD player Set-top box PC graphic card Game console HDMI picture performance quality enhancer module
Ordering information
Table 1. Ordering informationIP4777CZ38 TSSOP38 plastic thin shrink small outline package: 38 leads;
body width 4.4 mm; lead pitch 0.5 mm
SOT510-1
IP4777CZ38/V
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection Functional diagram
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection Pinning information
6.1 Pinning
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection
6.2 Pin description
Table 2. Pin descriptionVCC(5V0) 1 1 supply voltage for DDC and hot plug
circuits
ENABLE 2 2 enable input for DDC and hot plug
circuits
GND 3 3 ground for DDC, hot plug and CEC
circuits
TMDS_D2+ 4 4 ESD protection TMDS channel D2+
n.c. 5 6 not connected
TMDS_GND 6 5 ground for TMDS channel
TMDS_D1+ 7 7 ESD protection TMDS channel D1+
n.c. 8 9 not connected
TMDS_GND 9 8 ground for TMDS channel
TMDS_D0+ 10 10 ESD protection TMDS channel D0+
n.c. 11 12 not connected
TMDS_GND 12 11 ground for TMDS channel
TMDS_CLK+ 13 13 ESD protection TMDS channel CLK+
n.c. 14 15 not connected
TMDS_GND 15 14 ground for TMDS channel
CEC_IN 16 16 CEC signal input to system controller
DDC_CLK_IN 17 17 DDC clock input to system controller
DDC_DAT_IN 18 18 DDC data input to system controller
HOT_PLUG_DET_IN 19 19 hot plug detect input from system
GPIO
HOT_PLUG_DET_OUT 20 20 hot plug detect output to HDMI
connector
DDC_DAT_OUT 21 21 DDC data output to HDMI connector
DDC_CLK_OUT 22 22 DDC clock output to HDMI connector
CEC_OUT 23 23 CEC signal outputto HDMI connector
TMDS_GND 24 25 ground for TMDS channel
TMDS_CLK− 25 24 ESD protection TMDS channel CLK−
n.c. 26 26 not connected
TMDS_GND 27 28 ground for TMDS channel
TMDS_D0− 28 27 ESD protection TMDS channel D0−
n.c. 29 29 not connected
TMDS_GND 30 31 ground for TMDS channel
TMDS_D1− 31 30 ESD protection TMDS channel D1−
n.c. 32 32 not connected
TMDS_GND 33 34 ground for TMDS channel
TMDS_D2− 34 33 ESD protection TMDS channel D2−
n.c. 35 35 not connected
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection[1] Type number IP4777CZ38/V is pin compatible with type number IP4776CZ38.
Limiting values[1] Connector side pins:
TMDS_D2+, TMDS_D2−, TMDS_D1+, TMDS_D1−, TMDS_D0+, TMDS_D0−
TMDS_CLK+, TMDS_CLK−
CEC_OUT
DDC_DAT_OUT and DDC_CLK_OUT
HOT_PLUG_DET_OUT
[2] Board side pins:
CEC_IN
DDC_DAT_IN and DDC_CLK_IN
HOT_PLUG_DET_IN
ENABLE
GND 36 36 ground for DDC, hot plug and CEC
circuits
VCC(3V3) 37 37 supply voltage for CEC circuit
TMDS_BIAS 38 38 bias input for TMDS ESD protection.
This pin must be connected to a
0.1 μF capacitor.
Table 2. Pin description …continued
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage GND − 0.5 5.5 V input voltage input pins GND − 0.5 5.5 V
VESD electrostatic discharge
voltage
connector side pins (to ground);
IEC 61000-4-2, level 4 (contact)
[1] −8+8 kV
board side pins;
IEC 61000-4-2, level 1 (contact)
[2] −2+2 kV
Ptot total power dissipation DDC operating at 100 kHz - 14 mW
Tstg storage temperature −55 +125 °C
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection Static characteristics[1] This parameter is guaranteed by design.
Table 4. TMDS protection circuitTamb = 25 °C; unless otherwise specified.
Zener diodeVBRzd Zener diode breakdown
voltage
I = 1 mA 6 - 9 V
Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9
positive transient - 2.4 - Ω
negative transient - 1.3 - Ω
Protection diodeIbck back current from pins TMDS_x to pin TMDS_BIAS;
VCC(5V0) =0V; VCC(3V3) =0V 0.1 1 μA
IL(r) reverse leakage current VI = 3.0V - 1 - μA forward voltage - 0.7 - V
VCL(ch)trt(pos) positive transient channel
clamping voltage
VESD=8 kV per IEC 61000-4-2;
voltage30 ns after trigger -V
TMDS channel: pins TMDS_xCch(TMDS) TMDS channel capacitance VCC(5V0) = 5 V; f = 1 MHz; Vbias= 2.5V [1]- 0.7 - pF
ΔCch(TMDS) TMDS channel capacitance
difference
VCC(5V0) = 5 V; f = 1 MHz; Vbias= 2.5V [1]- 0.05 - pF
Cch(mutual) mutual channel capacitance between signal pin TMDS_x and
pin n.c.; VCC(5V0)=0 V; f = 1 MHz;
Vbias= 2.5V
[1]- 0.07 - pF
Table 5. DDC circuitVCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Supplies: pins VCC(5V0) and VCC(3V3)VCC(5V0) supply voltage (5.0V) connector side 4.5 5.0 5.5 V
VCC(3V3) supply voltage (3.3V) board side 2.7 3.3 5.5 V
ICC(5V0) supply current (5.0V) VCC(5V0) = 5.5V;
both channels HIGH:
DDC_DAT_OUT= VCC(5V0);
DDC_CLK_OUT = VCC(5V0) 1.4 2.5 mA
VCC(5V0) = 5.5 V;
both channels LOW:
DDC_DAT_IN= GND;
DDC_CLK_IN= GND;
DDC_DAT_OUT= open;
DDC_CLK_OUT = open 1.4 2.5 mA
ICC(3V3) supply current (3.3V) no pull-up resistor
connected to VCC(3V3) - 0.1 μA
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection
Board side: pins DDC_CLK_IN and DDC_DAT_INUsed as input
VIH HIGH-level input voltage - 410- mV
VIL LOW-level input voltage - 400- mV
IIL LOW-level input current VI = 0.2V - - 70 μA
VIK input clamping voltage II = −18 mA - - −1.2 V
ILI input leakage current VI = 3.6V - - ±1 μA input capacitance VI = 3 V or 0V
VCC(3V3) = 3.3V - 6 7 pF
VCC(3V3) = 3.0V - 6 7 pF
Used as output
VOL LOW-level output voltage IOL = 100 μA or 3 mA - 700- mV
IOH HIGH-level output current VO = 3.6V - - 10 μA output capacitance VI = 3 V or 0V
VCC(3V3) = 3.3V - 6 7 pF
VCC(3V3) = 3.0V - 6 7 pF
Connector side: pins DDC_CLK_OUT and DDC_DAT_OUTUsed as input
VIH HIGH-level input voltage 0.7 × VCC(5V0)- 5.5 V
VIL LOW-level input voltage −0.5 - 0.3 × VCC(5V0) V
IIL LOW-level input current VI= 0.2V - - 1 μA
VIK input clamping voltage II = −18 mA - - −1.2 V
ILI input leakage current VI = 3.6V - - ±1 μA input capacitance VI = 3 V or 0V
VCC(3V3) = 3.3V - 8 10 pF
VCC(3V3) = 3.0V - 8 10 pF
Used as output
VOL LOW-level output voltage IOL = 100 μA or 6 mA - 200- mV
IOH HIGH-level output current VO = 3.6V - - 10 μA output capacitance VI = 3 V or 0V
VCC(3V3) = 3.3V - 8 10 pF
VCC(3V3) = 3.0V - 8 10 pF
Table 5. DDC circuit …continuedVCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection[1] This parameter is guaranteed by design.
[1] The ENABLE pin has to be connected permanently to VCC(3V3) if no enable control is needed.
Table 6. CEC circuitVCC(3V3) = 2.7 V o 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Board side: input pin CEC_INCI(ch-GND)(levsh) level shifting input capacitance
from channel to ground
VCC(3V3) = 0 V; f = 1 MHz;
Vbias= 2.5V
[1]- 1416pF
SRr rising slew rate VI > 1.8V - 10 - mV/μs
N-FETΔVon on-state voltage drop N-FET state = on;
VCC(3V3)= 2.5 V; VS= GND;
IDS =3mA 125 140 mV
Connector side: output pin CEC_OUTILO output leakage current Vbias= 3.6V - - 0.1 μA
Rdyn dynamic resistance I = 1 A; IEC 61000-4-5/9
positive transient - 2.4 - Ω
negative transient - 1.3 - Ω
VCL(ch)trt(pos) positive transient channel
clamping voltage
VESD=8 kV per IEC 61000-4-2;
voltage 30 ns after trigger;
Tamb =25°C -V
Table 7. Enable circuitVCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Board side: input pin ENABLE[1]VIH HIGH-level input voltage HIGH = enable 0.7 × VCC(3V3) -VCC(3V3) + 0.5 V
VIL LOW-level input voltage LOW = disable −0.5 - 0.3 × VCC(3V3) V
IIL LOW-level input current VI = 0.2V;
VCC(3V3)= 5.5V
-10 - μA
ILI input leakage current Vbias= 3.6V −1 +0.1 +1 μA input capacitance VI = 3 V or 0V - 3 7 pF
Table 8. Hot plug control circuitVCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Board side: input pin HOT_PLUG_DET_OUTVIH HIGH-level input voltage - 1.9 - V
VIL LOW-level input voltage - 200 - mV
IIL LOW-level input current pull-down current to ground; =2V; VCC(5V0) = 5.5 V
-10 - μA input capacitance VI = 3 V or 0V - 6 7 pF
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection Dynamic characteristics[1] Typical values are measured at VCC(3V3) = 3.3 V, VCC(5V0) = 5.0 V and Tamb = 25°C.
[2] The ENABLE pin should only change when the DDC bus is in an idle state.
Connector side: output pin HOT_PLUG_DET_INVIH HIGH-level output voltage - VCC(3V3) -V
Table 8. Hot plug control circuit …continuedVCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Table 9. DDC circuitsVCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
Board side to connector side; see Figure4Pins DDC_CLK_IN to DDC_CLK_OUT and DDC_DAT_IN to DDC_DAT_OUT
tPLH LOW-to-HIGH propagation delay [1] 275 300 325 ns
tPHL HIGH-to-LOW propagation delay [1] 195 210 225 ns
Pins DDC_CLK_OUT and DDC_DAT_OUT
tTLH LOW to HIGH transition time RL =1.35 kΩ; CL = 50pF 90 110 130 ns
tTHL HIGH to LOW transition time [1] 135ns
Connector side to board side; see Figure5Pins DDC_CLK_OUT to DDC_CLK_IN and DDC_DAT_OUT to DDC_DAT_IN
tPLH LOW-to-HIGH propagation delay 110 130 150 ns
tPHL HIGH-to-LOW propagation delay [1] 20 30 40 ns
Pins DDC_CLK_IN and DDC_DAT_IN
tTLH LOW to HIGH transition time 100 120 140 ns
tTHL HIGH to LOW transition time [1] 235ns
Enable: pin ENABLEtsu set-up time pin ENABLE = HIGH before start
condition
[2] 100 - - ns hold time pin ENABLE = HIGH after stop
condition
[2] 100 - - ns
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection
NXP Semiconductors IP4777CZ38
DVI and HDMI interface ESD protection
10. Application information
10.1 TMDSTo protect the TMDS lines and also to comply with the impedance requirements of the
HDMI specification, the IP4777CZ38 provides ESD protection with a low capacitive load.
The dominant value for the TMDS line impedance is the capacitive load to ground. The
IP4777CZ38 has a capacitive load of only 0.7 pF.
10.2 DDC circuitThe DDC bus circuit contains full capacitive decoupling between the HDMI connector and
the DDC bus lines on the PCB. The capacitive decoupling ensures that the maximum
capacitive load is within the 50 pF maximum of the HDMI specification.
The slew rate accelerator supports high capacitive load on the HDMI cable side. Various
HDMI cable suppliers produce low-cost and long (typically 25 m) HDMI cables with a
capacitive load of up to 6 nF.
The slew rate accelerator boosts the DDC signal independent of which side of the bus is
releasing the signal. The DDC circuit providesa level shifting option. The ENABLE signal
is enabling and disabling the complete DDC buffer.
