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INS8251NNSCN/a6avai7 V, programmable communication unterface


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INS8251N
7 V, programmable communication unterface
National
[ Semiconductor
November 1980
INSB251 Programmable Communication Interface
General Description 'r,r; " rr
The 1NS8251 is a programmable Universal Synchronous/
Asynchronous Receiver/Transmitter (USART) chip
contained in a standard 28-pin dual-in-line package. The
chip, which is fabricated using N-channel silicon gate
technology, functions as a serial data input/output
interface in National Semiconductor's N8080 micro-
computer family. The functional configuration of the
INS8251 is programmed by the system software for
maximum flexibility, thereby allowing the system to
receive and transmit virtually any serial data communica-
tion signal presently in use (including IBM Bisync).
The INS8251 can be programmed to receive and transmit
either synchronous or asynchronous serial data. The
INS8251 performs serial-to-parallel conversion on data
characters received from an input/output device or a
MODEM, and parallel-to-serial conversion on data
characters received from the CPU. The CPU can read the
complete status of the INS8251 at any time during the
functional operation. Status information reported
includes the type and the condition of the transfer
operations being performed by the INS8251, as well as
any transmission error conditions (parity, overrun, or
framing).
Features
. Synchronous and Asynchronous Full Duplex
Operations
. Synchronous Mode Capabilities
- Selectable s, to 8-Bit Characters
- Internal or External Character Synchronization
- Automatic Sync Insertion
q Asynchronous Mode Capabilities
- Selectable 5. to 8-Bit Characters
- 3 Selectable Clock Rates (1x, 16x or 64x the
Baud Rate)
- Line Break Detection and Generation
- 1-, ly2-, or 2-Stop Bit Detection and Generation
- False Start Bit Detection
. Baud Rates
- DC to 56k Baud (Synchronous Mode)
- DC to 9.6k Baud (Asynchronous Mode)
. Transmission Error Detection Capabilities
- Parity
- Overrun
- Framing
. Double Buffering of Data
. TTL Compatible
q Single TTL Clock
q Reduces System Component Count
. MICROBUSTM' Compatible
IN88251 MICROBUS Configuration
'Trademark, National Semiconductor Corp.
--'---RxRtrY
, TXRDV
SERIAL
M-Di) DATA DUI
ADDRESS <=> D7-0tl no r
M msnzsi SERIAL
A I RESET DATA m " " -232
cpu oars C RESET mm --- INTERFACE
GROUP R I/OR - - EIA <=>
o = RD DTR = DRIVERS
CONTROL B - -
I/uw - '
o -..er- wn RTS '
S E - BE --
7 cs -
An A CTS ----
---i cm
m "XI:
5 ca ' ,
BAUD scC7
GENETJKETDR 003642
_ 1980 National Semconoucim Corp
I tiF2G-FL5Mt10/F'rm1etf in USA
aoepam uoneagunwwoo alqewwmfioxd ngssm
t5teit;
Absolute Maximum Ratings
Ambient Temperature Under Bias .............. 0°C to +70°C
Storage Temperature .................... -65c'C to +150°C
Voltage on Any Pin with Respect to Ground ...... -0.5 V to +7 V
Power Dissipation ............................. 1 Watt
Note: Maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under
dc electrical characteristics.
DC Electrical Charactetistics
TA = 0°C to +7tf'C; Vcc = 5.0 vi 5%) GND = ov
Symbol Parameter Min Typ Max Unit Test Conditions
I/c Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 Vcc V
VOL Output Low Voltage 0.45 V ' = 1.6 mA
VOH Output High Voltage 2.4 V lors = -100YA
IDL Data Bus Leakage -50 pA VOUT = 0.45 V
10 PA VOUT = VCC
IIL Input Leakage 10 PA VIN = Vcc
ICC Power Supply Current 45 80 mA
Capacitance
TA = 25°C: Vcc = GND = 0V
Symbol Parameter Min Typ Max Unit Test Conditions
CIN Input Capacitance 10 pF fc = 1 MHz
CI/O l/O Capacitance 20 pF Unmeasured pins returned to GND.
Test Load Circuit
Typical A Output Delay vs. A Capacitance (pF)
" ww'''''
5109 ',-'is'- "
2 a SPEC.
nEVIcE ,
UNDER =
TEST 'd
Ct" 2n /
= = -20 ,
-100 Hill 0 +50 +1uu
A CAPACITANCE (pF)
AC Electrical Characteristics
TA = 0°C to +70''C; Vcc = 5.0V , 5%; GND = OV
Symbol Parameter Min Max Unit Test Conditions
BUS PARAMETERS (Note 1)
Read Cycle
(AR Address Stable Before FEAT: (CS. C/E) 50 ns
tRA Address Hold Time for Tt"7ro (tS, C/B) 5 ns
tan R-tar, Pulse Width 430 f ns
tRD Data Delay from FTr7iTy (3? ns Cc = 100 pF
tDF RE-Aff to Data Floating 200 ns th. = 100 pF
25 ns CL = 15 pF
lav Recovery Time Between WRITES (Note 2) 6 tcy
Write Cycle
tAW Address Stable Before wit-E 20 ns
tWA Address Hold Time for WR-ITE 20 ns
tww Wmrrg Pulse Width 400 ns
tDW Data Set-Up Time form 200 ns
tWD Data Hold Time form 40 ns
OTHER TIMINGS "s
Icy Clock Period (Note 3) 0.4/29.) 1.35 ps
tow Clock Pulse Width 220 0.7 tCY ns
IR, " Clock Rise and Fall Time 0 50 ns
tDTx TxD Delay from Falling Edge ofTTtSRx Rx Data Set-Up Time to Sampling Pulse Wi CL = 100 pF
tHRx Rx Data Hold Time to Sampling Pulse ps CL = 100pF
fr, Transmitter Input Clock Frequency
1x Baud Rate DC 56 kHz
16x and 64x Baud Rate DC 520 kHz
tpr Transmitter Input Clock Pulse Width
1x Baud Rate 12 tcy
16x and 64x Baud Rate 1 1 my
two Transmitter Input Clock Pulse Delay 1
1x Baud Rate 1 15 tCY
16x and 64x Baud Rate 3 Icy
fax Receiver Input Clock Frequency
Ix Baud Rate DC 56 kHz
16x and 64x Baud Rate DC 520 kHz
tRpw Receiver Input Clock Pulse Width
1x Baud Rate 12 tcy
16x and 64x Baud Rate 1 tcy
tHPD Receiver Input Clock Pulse Delay
1x Baud Rate 15 tcy
16x and 64x Baud Rate 3 tcy
th TxRDY Delay from Center of Data Bit 16 Icy CL = 50 pF
tRx RxRDY Delay from Center of Data Bit 20 toy
US Internal SYNDET Delay from Center of Data Bit 25 tcy -
tES l, Internal SYNDET Set-Up Time Before Falling Edge of TRE 16 Icy
thE I TxEMPTY Delay from Center of Data Bit 16 Icy CL = SOpF
twc Control Delay from Rising Edge ofWRITE (TxE,5TirtT;) 16 tcy
tcn ; Control to ii-g/V, Serup Time (m, m) 16 tcy
NOTES:
1. AC timings measured at VOH = 2.0 v, VOL = 0.8 V, and with test load Circuit of page 2.
2. This recovery time IS for initialization only, when MODE, SYNC1. SYNC2, COMMAND and first DATA BYTES are written into the USART.
Subsequent wrmng of both COMMAND and DATA are only allowed when TxRDY =1.
3. The TxC and FixC frequencies have the following limitations wim respect to CLK:
for 1x Baud Rate, fo or fn, $1/30lcy1
for 16x and 64x Baud Rate,f1-x or (RX $1/4.5(Cy1
' Reset Pulse Width = 6 my minimum.
Timing Waveforms
READ AND WRITE TIMING tCY
cm ag, C N / N
'WRITE AND READ PUlSES
HAVE NO TIMING LlhtlTATR1N
WITH RESFEBY TO ELK.
tVx---]
'C-TS '
V-tes,
TRANSMITTER CLOC K
AND DATA
t"x_8tiuio)
16 TxC PERIODS
T%(tiix BAUD)
Tsto-Mu--- ____X::::
RECEIVER CLOCK
AND DATA
‘SRX THRX
mt, A BAUD)
INTERNAL m RPO
SAMPLING n
START BIT ----- Ist DATA BIT ----
RID J -
G-CtNxiutum
INTERNAL l‘BRxC PERIODS>+<71G 31c ''Emoirs----l
SAMPLING n L
Tx RDY AND Rx RDY
TIMING (ASYNC MODE)
mu I START an , DATA ans IPARITY BIT] STOP an 1 START arr I
Rx ROY
n EMPTY -1.
Tx ROY 5
WRITE LI
WRITE lst BYTE WRITE 2nd BYTE want am an:
“D MARKINGI START an I DATA an Irwnry an] STO? an I START BIT I-"--
F-------, DATA "re--------]-- 2nd DATA BYTE
INTERNAL SYNC DETECT
F----syNc "ArtAcT"m110u"m--------i
mo I lu BIT I I I I LAST BIT
SVNDET EWRESET "
(OUTPUT) SOFTWARE
COMMAND
EXTERNAL SYNC DETECT
SYNOET
(INPUT) -----_
INSB251 Block Diagram
INTERNAL
DATA BUS
READ/WRITE
CONTROL
CONTROL
z: n O a
*141" “I
u: u, :n :0
POWER _ Hill
sumv _1. GNO
NOTE: APPLICABLE PINOUT NUMBERS
ARE INCLUDED WITHIN
PARENTHESES.
TRANSMIT
BUFFER Tx0
TRANSMII (18)
CONTROL th
RECEIVE
aurpea Rx0
RECEIVE -
CONTROL Rxtl
SVNDET
INS8251 Functional Pin Definitions
The following describes the function of all the INS8251
input/output pins. Some of these descriptions reference
internal circuits.
INPUT SIGNALS
Chip Select (F33): When low (logic 0), the chip is selected.
This enables communication between the INS8251 and
the INSBOBOA microprocessor.
Read (EB): When low, allows the INSBOBOA to read
data or status information from the INS8251.
Write (Cm").. When low, allows the INS8080A to write
data or control words into the INS8251.
Control/Data (C/B): Used in conjunction with an active
RD or WR input (logic 0) to determine overall device
operation as indicated below.
c-s cm is W Operation
0 0 0 1 Data character read from |N$8251
0 0 1 0 Data character written Into INS8251
0 1 0 1 Status information read from INS8251
0 1 1 0 Control word written into INS8251
1 x x x Device not selected i
Reset: When high (logic 1), places the INS8251 in the
idle mode. The device remains in this mode until a new
set of control words is written into the INS8251 to
program its functional definition. Minimum Reset pulse
width is Btcy.
Clock (CLK): TTL clock that is used to generate internal
timing signals for the INS8251. The minimum frequency
of the CLK input is 30 times the receiver/transmitter
clock frequency for the synchronous mode, and 4.5
times the receiver/transmitter clock frequency for the
asynchronous mode. The CLK input is normally connec-
ted to the ()2 (TTL) output of the INS8224 Clock
Generator and Driver device,
Transmitter Clock (TIC): This clock input controls the
rate at which a data character is to be transmitted. The
frequency of the TxC input is equal to the Baud Rate
for the synchronous mode, and is a multiple (1x, 16x or
64x) of the Baud Rate for the asynchronous mode. A
portion of the Mode Instruction Word (see figure) selects
the value of the Baud Rate Factor when in the asynch-
ronous mode. Transmitter Data are clocked out of the
INS8251 on the falling edge of the TE input.
Data Set Ready (tTs-R).. General-purpose input whose
condition can be tested by the INSBOSOA using a status
read operation. However, a Iow-levei DSR input is
normally used to test data set ready conditions.
Clear to Send (m): If low when the TxEN bit (D0) of
the Command Instruction Control Word (see figure) is
set high, enables the INS8251 to transmit serial data.
Receiver Data (RxD): Serial data input from a MODEM
or an input/output device.
Receiver Clock (Ex-C).. This clock input controls the rate
at which a data character is to be received. The frequency
and selection of the ETC input is as described above for
the "ix-c input. Receiver data are clocked into the
INS8251 on the rising edge of the Fre input.
Vcc: +5-volt su pply.
Ground: O-volt reference.
OUTPUT SIGNALS
Data Terminal Ready (m): General-purpose output
which can be set to an active low by programming the
D_T§ bit (DI) of the Command Instruction Control
Word. However, a low-level DTR output is normally
used for data terminal ready or rate select control.
Request to Send (wi).. General-purpose outpuwich
can be set to an active low by programming the RTS bit
(D5) of the Command Instruction Control Word.
However, the RTS output is normally used for request
to send control in the transmit mode.
Transmitter Data (TxD): Composite serial data output
to a MODEM or input/output device. The TxD output
is held in the marking state (logic 1) upon 3 Reset
operation.
Transmitter Ready (TxRDY); When high, alerts the
INS8080A that the transmitter is ready to accept a data
character. The TxRDY output, 'which is automatically
reset whenever a character is written into the INS8251,
can be used as an interrupt to the system. For polled
operation, the condition of the TxRDY signal can be
tested try the INS8080A using a status read operation.
Transmitter Empty (TxE): Goes high to indicate the end
of a transmit mode. The TxE output is automatically
reset whenever a character is written into the INS8251.
In the synchronous mode, a high-level TxE output
indicates that a character has not been loaded, the trans-
Pin Configuration
mitter buffer is empty, and the sync character(s) of a
data block are soon to be transmitted automatically as
fillers.
Receiver Ready(RxRDY): When high, alerts the
INS8080A that the receiver contains a data character
that is ready to be input to the CPU. The RxRDY
output, which is automatically reset whenever a char-
acter is read from the INS8251, can be used as an
interrupt to the system. For polled operation, the
condition of the RxRDY signal can be tested by the
INS8080A using a status read operation.
INPUT/OUTPUT SIGNALS
Data (Da- Do) Bus: This bus compriseseightTRlSTATE®
input/output lines. The bus provides bidirectional
communications between the INS8251 and the
INS8080A. Data are routed to or from the internal data
bus buffer upon execution of an INS8080A OUT or
+ instruction, respectively. In addition, control words,
command words and status information are transferred
through the data bus buffer.
Sync Detect (SYNDET): This pin may be used in the
synchronous mode only, System software can program
SYNDET as either an input or an output. When used as
an output (internal sync detect mode), a high-level
SYNDET indicates that the INS8251 has detected sync
character(s) in the received serial data. The SYNDET
output is automatically reset upon a status read opera-
tion by the INS8080A. When used as an input (external
sync detect mode), a high-level SYNDET causes the
INS8251 to start assembling data characters on the
falling edge of the next RxC input.
IN88251 Programming
The system software uses a Mode Instruction Control
Word and a Command Instruction Control Word (see
figures) to establish the complete functional definition
of the INS8251. These control words must immediately
follow an internal or external reset operation. Once the
Mode Instruction Control Word has been written into
the INS8251 by the CPU, sync characters (when applic-
able) or Command Instruction Control Words may be
inserted as shown in the typical data block transfer
diagram.
1 28 -01
03 -t 27 --oty
"KO --" 3 N -1lcc
GND - a 25 -lix-c
" - 5 " --m
" - Ii 23 ...-tts
ns ---7 22 -tTsTt
07 - a INS8251 21 --RESET
1T: - 9 20 -CLit
i7gTt - w 19 -Tx0
t_S - ll in -TXEMPTY
Mi - 12 17 -Ws"
kT: - 13 la r-SYNOET
RXRDV - 14 15 -TxRDY
Registered Nimoritii Semiconductor Cin
m as 05 04 tn " ill no
'----z---" EVEN PARITY
no ursrop ans 6 PAN" N/ ENABLE: I I
. -. ENERATIU - CHARACTER aAun RATE
_ 1 - ENABLE
on = INVALID cum. 0 . mm,“ LE GTH: FACTOR:
m = IBIT 1 f EVEN M = sans on = svncmuns
lil ' mans 0 - ODD n1 = saITS U1 = X1
11 = 23th 10 = 7BITS m = x15
11 = sans n = xsa
ASYNCHRONOUS MODE
" Da " D4 " " D1 Do
SINGLE EXTERNAL EVEN PARITY
CHARACTER SYNC PARITY ENABLE: I ,
SYNC; DETECT: "Ir/g/y/ 1 _ ENABLE CHARACTER SYNC MODE; an
1 = SINGLE 1 = svmnn C _ u a DISABLE LENGTH:
SYNC ISAN 1 --- EVEN on = EBITS
CHARACTER INPUT il --" con M - sans
ll = DOUBLE u = SYN0ET
SYNC IS AN 10 T 7i1ITS
CHARACTER ouwur 11 = il ans
mode instruction control word format
SYNCH RONOUS MODE
D7 De 05 m 03 " DI Do
ENTER INTERNAL REQUEST ERROR SEND RECEIVE DATA TRANSMlT
HUNT RESET m SEND RESET BREAK ENABLE TERMINAL ENABLE
MODE (IR): (RTS): (ER): CHARACTER (Rm: READY mm):
(EH): l "ATI"" l-r=st'/l/fltf l i,Ith"s l “E2235 1 ' ENA8LE TJL, 1 = ENlt8LE
1 : ENABLES 51 T . _ - = =
SEARCH MODE LOW & FE Txt) OUTPUT , - 9'5”” lr;-, 00TPOT il D'SAELE
son SYNC msmucnon ERROR Low LOW
CHARACTERS wonn FORMAT FLAGS o _ NORMAL
OPERATION
command instruction control word format
MODE INSTRUCTION WORD
cm = "1" SYNC CHARIWTER1 svwnunowuus MODE
SYNC CHARACTER l ONLY (SEE NOTE)
COMMAND msmucnow wono
- - " DATA
cm - il C8ARACTER(s) NOTE:
WHEN me MODE msmucnow
cm = 1 COMMAND IhlSTR0CTlOlil wono l'fl8slrl 'l1'l"etrlt? THE
CHARACTER (BIT 07 ' "I"),
mi - "a" DA” iff/if/Iyer/hyd
CHARACTERW) iiiriiiifsiii; ARE OMITTED
m ms ASYNCRR0N00S mans.
cm _ '1 COMMAND msmucnou WORD
typical data block transfer
|N88251 Programmable Communication Interface
IN38251 Status
interrupt driven environment.
The INS8251 has provisions for allowing the programmer to read the status of the device at any time during the
functional operation. When the cm input is a high- "level, a normal read operation is executed to read this status
information. The figure below shows the bits in the Status Read Word format. Since some of the status word bits
have identical meaning to external output pins, the INS8251 can be used in a completely polled environment or in an
Order Number INS8251d
N.S. Package Number J28A
28-Lead Plastic Dual-in-Line Package [Cerdip (J)]
07 De 05 D4 [13 B2 01 Do
MR SY NDET FRAMING 0VERR0N PARITV us many TxHDV
(SEE NOTE) (SEE NOTE) E(nrrgm Wye E(RPRSJR (SEE mum (SEE NOTE) (SEE NOTE)
I = VALID I = CPO = mun
STOP BIT DOES NOT ERROR
DEYECTED READ A DETECTED
AT END CHARACTER _
OF EVERY BEFORE 0 - WHEN
CHARACTER NEXT ONE E" 3” 0F
BECOMES MANO NOTE:
0 = WHEN AVAILABLE msmucnou ans nu.nz, m; a m
(E0155; 0 = WHEN 'YT"' “AVE IDENTICAL
COMMAND ER an or [r/#lM,igl TO EXTERNAL
INSTRUCTION COM MA
WORDIS INSTRUCTION
A"I" WORD Is
"T-----'
FE. OE a. PE FLAGS no
NOT IIIimaIT THE OPERATION
OFTHE INSBZEI
status read word format
Physical Dimensions
.mm ,1
'T.) ' m: "ld) mm
‘Illlrlllni m” l mm“ (Inn 'if"
, [itvv-,,av,,r,,r,,,,,,rm,,,
- 1JLrrLrEr0rCrCrCrWlrErE'rTTrF,
um mm.
5:32,"; - 'il'" W - -n"i',',-,','l'i, "rr' "1’? am
_ .I. m. "I/h" um 'No .. ...I
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i"e, "rt I iii''] g I I ' ' l,
J,',',',,',",',, o'', -, - «I - JK', , am',',',,',' o..,'',',',',,) I J d,,
3312:: I222 :22 1:123:22. M - ".1; .- J,',',' 31;;- - - - ""' -- '' 1e nu"?
28~Lead Molded DIP (N)
Order Number IN88251N
N.S. Package Number N28A
Natiortal Semicondrrztar
Corporalmn
3900 ‘Sr‘nwondm lm DWI.
$qu cm. CA 9mm
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Telex $8096
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INS8251J - product/ins8251j?HQS=TI-nulI-nu|I-dscatalog-df-pf-nulI-wwe
INS8251 N - product/in38251n?HQS=T|-nu|I-null-dscatalog-df—pf-nu||-wwe
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