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INS1771N-1 |INS1771N1NSN/a50avai20V, floppy disk formatter/controller


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INS1771N-1
20V, floppy disk formatter/controller
S-to! EL,
T '3935'
April 1977
Pub. No. 426305468-001
|NS1771-1 Floppy Disk Formatter/Controller
General Description
The INSI 771-1 is a programmable fioppydisk formatter/
controller chip contained in a standard 40-pin dual-in-
line package. The chip, which is fabricated using
N-charmel silicon gate technology, interfaces a floppy
disk drive directly to a computer interface bus. The
INS1771-1 provides soft sector formatting, which may
be either IBM 3740 compatible or a user-selected sector
format.
The |N51771-1 is designed to operate on a multiplexed,
TRl-STATE® 8-bit bidirectional bus with other bus-
oriented devices. The chip is programmed by the system
software via the bus and all data, status information, and
control words are transferred over the bus lines,
Features
. Soft Sector Format Compatibility
I Automatic Track Seek with Verification
0 Provisions for Miniature Floppy Disk Interface
. Read Mode Capabilities
- Single/Multiple Record Read with Automatic
Sector Search or Entire Track Read
- Selectable 128-Byte or Variable Record Length
O Write Mode Capabilities
- Single/Multiple Record Write with Automatic
Sector Search
- Entire Track Write for Diskette Initialization
. Programmable Controls
- Selectable Track-to-Track Stepping Time
- Selectable Head Settling and Head Engage Times
- Selectable Three Phase or Step and Direction and
Head Positioning Motor Controls
. Double Buffering of Data
. TTL Compatible
0 DMA or Programmed Data Transfers
. Reduces System Component Count
. On-Chip CRC Generation and Checking
0 Direct Plug-in Replacement for Western Digital
FD1771
lNS1771-1 General System Configuration
PARALLEL/
SERIAL
INTERFACE
svsnm S
PROCESSOR _'''"'
f wan:
' FO DATA
C FLBPPY
T FO CLOCK pm;
I: nmmc '
C CONTROL
MEMORY
9 1977 National Semiconductor Corp.
f taA.f32thMa7/Prirtted m U.$.A.
Iannnunn/Ia'npuunJ \IQII'I Kdrlnu |-| I I noun
Absolute Maxim um Ratings
VDD with Respect to VBB (Ground) .......... +20V to -0.3 V
Max Voltage to Any Input with Respect to VBB- . .+20 V to -0.3 V
Operating Temperature ..................... 0°C to +70°C
Storage Temperature .................... -55°C to +125°C
Note: Maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under
dc electrical characteristics.
DC Electrical Characteristics
TA = 0°C to +70°C, VDD = +12.0v t 0.6 v, veg = -5.0v t 0.5V, Vss = ov, Vcc = +5 v i 0.25v, IDD =10mA
nominal, ICC = 30 mA nominal, IBB = 0.4 nA nominal.
Symbol Characteristic Min Typ Max Unit Conditions
'Ll Input Leakage 10 PA VIN = VDD
ILO Output Leakage 10 yA VOUT = VDD
VIH [ Input High Voltage 2.6 V
VIL Input Low Voltage (All Inputs) 0.8 V
VOH Output High Voltage 2.0 V IO = -100PA
VOL Output Low Voltage GAE V IO = 1.6 mA
Note: VOL :2 0.4 V when interfacing with Iow-power Schottky parts (lo < 1mA).
AC Electrical Characteristics
TA = 0°C to +70°c, VDD = +12v t 0.6V, v33 = -5V , 0.25 v, VSS = OV, VCC = +5v , 0.25v.
Symbol l Characteristic I Min I Typ l Max l Unit Conditions
Read Operations
tET Setup ADDR a O_S to FTE- 100 ns
tHLD Hold ADDR & eg from FE 10 ns
IRE "irE- Pulse Width 500 ns CL = 25 pF
IDRR DRQ Reset from iiT? 150 ns
HRH INTRO Reset from FE 3000 ns
IDACC Data Access from R-g 450 ns CL = 25 pF
tDOH Data Hold from 're 50 150 ns CL = 25 pF
Write Operations -
[SET Setup ADDR & t5gtow-E 100 ns
tHLD Hold ADDR atrstromihrE 10 ns
tWE m Pulse Width 350 ns
IDRR DRQ Reset frumvr/E- 150 ns
tIRR INTRO Reset from m 3000 ns (see note)
tDS Data Setup tovVE" 250 ns
tDH Data Hold from m 150 ns
AC Electrical Characteristics (cont.)
TA = 0°C to +70°C, VDD = +12V , 0.6V, V83 = -51/ t 0.25V, vss = 0V, VCC = +5V i 0.25 V.
Symbol L Characteristic l Min I Typ I Max I Unit Conditions
External Data Separation (RYriii = o)
Ipwx Pulse Width Rd Data & Rd Clock 150 350 ns
tCX Clock Cycle Ext 2500 ns
IDEX Data to Clock 500 ns
tDDX Data to Data Cycle 2500 ns
Internal Data Separation (rTTii = 1)
tpwl Pulse Width Data & Clock 150 1000 ns
TCI Clock Cycle Internal 3500 5000 ns
Write Data Timing
tWGD Write Gate to Data 1200 ns 300 ns i CLK tolerance
thw Pulse Width Write Data 500 600 ns
tCDW Clock to Data 2000 ns 10.5% i CLK tolerance
tCW Clock Cycle Write 4000 ns 10.5% i CLK tolerance
WVGH Write Gate Hold to Data 0 100 ns
Miscellaneous Timing
tCDI Clock Duty 175 ns 2MHz i 1% (see note)
ICD2 Clock Duty 210 ns
tSTP Step Pulse Output 3800 4200 ns
IDI R Dir Setup to Step 24 us _
tMR Master Reset Pulse Width 10 us J,e,','(rtiT'rrt1',t,ef
tlp Index Pulse Width 10 us
MF Write Fault Pulse Width 10 us
Note: Timings are given for 2 MHz Clock. For those timings noted, values will double when chip is operated at 1 MHz.
Timing Waveforms
HBO VOL
A0111?”
l 4 Msss I
I --l [---mo, I _
-re F--' VOLT
(T, t--l
l mm »| 1+ VOL
I l VIL
DATA VALID (BTU
READ DATA
(Burrms TRISTATED)
'uLU)r,
tnACC (mm
NOTES:
.FSMAY " FEHMANENTLV TIED LIJWIF
DESIRED.
FOR READ TRACK COMMAND. THIS TIME MAY
BE 1210 32 psWHEN§= ll, (THISTIME
DOUBLES WHEN cut =1MHL)
Read Enable Timing
nnn VOL
A0,A1,E§”)
DATA VALID (m)
WRITE DATA
'L 2 32sss I
“>1 _ loan I
= una -I
l tsto-rl _ ilor
tSET _]
l-- log - f--
NOTES:
I, CE MAY BE PERMANENTLY TIED LllW IF
DESIRED.
2. WHEN WRITING DAIA INTO SECTOR, TRACK,
" BATA REGISTER, USER CANNOT READ
THIS REGISIER 0NTI T LEAST 8sss AFTER
THE RISING EDGE " W VWHEN WRITING INTO
THE COMMAND REGISTER, STATUS IS NOT
VALID UN1IL SOME 12m LATER. THESE TIMES
ARE DOUBLED WHEN ClK -- 1MH1.
Write Enable Timing
Timing Waveforms (cont.)
.4 PM“ -H F-trnvx -l I+wwx wag?
Fncmcxj rl IL l
I----- tct ----- --- tCX xmx
"lflly Ipwx .I Io lex .1 l" +1 F-
romm: l n rn FL
_ luEx Fluvwk iDEX - lcx --l
---- 'UDX
NOTES; .
1. ABOVE TIMES ARE DOUBlEDWHEN ELK _ I MHz,
2. CONTACT NSC FOR EXTERNAL CLOCK/MTA
SEFARATDR CIRCUITS.
Read Timing (XTDS = ol
fl -i'T 4% 4.pr
FODATA c
l--- to-----)--- tct
LEADING EDGE OF
DATA PULSE MUST
OCCUR IN SHADED
" m -el
NOTES:
1. INTERNAL DATA SEPARATION MAY WORK FOR
SOME APPLICATIONS. HOWEVER, FOR APPLICA-
YIONS REDUIHING HIGN DATA RECOVERY
RELIABILITY, NSC RECOMMENDS THAT EXTER-
NAL DATA SEPARATION BE USED.
t. FDCLDCK MOST " TIED HIGH.
Read Timing (XTDS = Il
gt...—
nvcn ---l F-
ws -..1
F- "NED -l (NM mm
wwwl _ -l F- -l wwwt F- +1 km
LTI m m rc"L-r?/t
F- lcnw _.} tow l low I
LAST DATA BIT
TO BE WRITTEN
Write Data Timing
TP T 11IH rsteriir'
STEFIN STEP ou1
mm: V0" '1-syze.co.-
W Ih‘wal ll vm 1517 tim' mp
-""l r--"- m Fad +01 k I-cr! _ F's”
- _ twr-A STEP VOL -"''-'"rL.J"L=""iruo...-
J-IU H" -l
c” -Lrt.-
41 tttrg
Miscellaneous Timing
INS1771-1 Block Diagram
(DAL l) - DAL "
DATA OUT
EUFFERS
-7r-T'
DATA COMMAND _ SECTOR TRACK - STATUS
REGISYER REGISTER REGISTER REGISTER - REGISTER
t (16)
DATA - FOCt0CK
DAYASHIFT .
- REGISTER - itl't (27!
I ATOR - meu
ALU t -
. (25) XTOS
wmtzoam 31)
(mmsx) -
DETECTOR
_ LOGIC
COMPUTER
INTERFACE
CONTROL
CONTROL
Von -.-e.i.1L.- 412v
Vcc -i21), MV
SUPPLIES vo...1-0...- -5v
vss -.it11-).- GNU
CONTROL
(190116)
CONTROL
v_nmsnp
Firtmtgg
CONTROL DISK
INYERFACE
CONTROL
NOTE APPLICABLE PINOLIT NUMBERS
ARE IleCtlJ0E0WlTHn8
FAR0THESES,
lNS1771-1 Functional Pin Definitions
The following describes the function of all INS1771-1
input/output pins. Some of these descriptions reference
internal circuits.
In the following descriptions, a low represents a
logic 0 (0 Volt nominal) and a high represents a
logic 1 (+5 Volts nominal).
INPUT SIGNALS
ChipSelect (a): When low, the chip is selected. This
enables communication between the INS1771-1 and the
Read Elable (iiTir. When low coincident with an active
(low) CS input, allows the CPU to read data or status
information from a selected register of the chip.
Functional Pin Definitions (cont.)
Write Enable (WE): When low coincident with an active
(low) CS input. allows the CPU to write data or control
words into a selected register of the chip.
Register Select (A0,A1) Lines: These two inputs_are
used in conjunction with either an active (low) RE or
WE input to select an INS1771-1 register to read from
or write into as indicated below.
A1 A0 Fig -v'iTE Selected Register
0 O 0 1 Status Register
0 0 i 1 0 Command Register
0 1 I o 1 .
Track Register
0 1 1 0 -
1 0 0 1 .
Sector Register
1 O 1 0
1 1 O 1 _
Data Register
1 1 1 0
Master ResetiWii).. When low, clears the Command
Register, resets bit 7 (Not Ready) of the Status Register
low, and makes the m/STEP output active low. When
the W returns high, a Restore command is executed
(regardless of the state of the Ready input from the
floppy disk drive).
Clock(CLK): This input pin requires a 2-megahertz
(t1%) squarewave clock as a reference for all internal
timing.
For a miniature floppy disk, a 1.MHz (i1%)
squarewave clock is required.
ExternalData Separator(XTDS): When low, the
composite read disk serial data (data bits and clock)
from the floppy disk drive is separated externally
by the user. When high or open, the composite read
disk data is separated by the internal data separator
of the chip.
Floppy Disk Date(FDDATA): This input pin pro-
vides either of the following serial data: both clock
and data bits (composite read disk data) when the
XTDS input is high; or externally separated data bits
when the XTDS input is low.
Floppy Disk Clock (FDCLK): This input pin provides
the externally separated clock when the XTDS input is
low. The FDCLK input should be connected to +5 Volts
(logic 1) when the XTDS input is high.
Write Protect (WPRT): When low, immediately ter-
minates a Write command and sets bit 6 (Record Type/
Write Protect) of the Status Register high. In addition,
an interrupt is generated when the WPRT input is low.
The WPRT input is sampled whenever a Write command
is received from the CPU.
Write Fault 1Tfpr.. When low coincident with an active
(high) Write Gate (WG) input, causes the current Write
command to be terminated and sets bit 5 (Record Type/
Write Fault) of the Status Register high. The W7 input
should be made inactive (high) coincident with an
inactive (low) WG input.
Index puIseiITy.. Goes low for 10 microseconds
(minimum) whenever an index mark is encountered
(once per revolution) on the diskette.
Track 00 (TROO): Goes low whenever the Read/Write
head is positioned over track 00 of the diskette.
Ready: When high before the execution of a Read or
Write command, indicates that the floppy disk drive is
ready for a Read or Write operation. When low, the
Read or Write operation is not performed and an inter-
rupt is generated. However, a Seek operation is always
performed. The complement of the Ready input appears
as bit 7 (Not Ready) of the Status Register.
Three-Phase Motor Select (W): When low, the three-
phase motor control interface is selected for the floppy
disk drive by the |NSI771-1. When high or open, the
step-direction motor control interface is selected by the
INS1771-1.
Disk Initialization (DINT): When low coincident with a
Write Track command from the CPU, causes the Write
Track operation to be terminated and bit 6 (Record
Type/Write Protect) of the Status Register to be set
Test: This input pin is normally tied to +5 Volts.
However, it may be used to disable the programmed
stepping rate delays for testing the lNS1771-1 or for
disk drives that do not require the long delay times to
change tracks. These delays are disabled by tying the
Test input to ground.
Head Load Timing(HLT): When high, the Read/Write
head is assumed to be engaged against the recording
medium (diskette). The HLT input is sampled after each
10 millisecond internal delay.
V33: -5 Volt supply.
Vcc: +5 Volt supply.
VDD: +12 Volt supply.
Vss: Ground (0 Volt) reference.
OUTPUT SIGNALS
Data Request (DRU): Open-drain output to the CPU
that goes high when the |NS1771-1 is ready to transfer
a byte of data during a Read or Write operation. The
DRCI output is reset low upon the completion of a byte
Read or Write operation.
Interrupt Request (INTRO): Open-drain output to the
CPU that goes high at the completion or termination of
any operation. The INTRO output is reset low when a
new command is loaded into the Command Register.
Write Data (WD): Composite write disk data (both clock
and data bits of 500 nanoseconds in duration) output
to the floppy disk drive. The WD output can drive two
TTL loads.
Write Gate (WG): Active (high) whenever data is to be
written on the diskette. As a precaution to erroneous
writing. the first data byte must be loaded into the Data
Register (in response to a DRQ output from the
iNS1771-1) before the WG output can be activated.
Functional Pin Definitions (cont.)
Track Greater Than 43 (TG43): When high during a
Read or Write operation, informs the floppy disk drive
that the Read/Write head is positioned between tracks
44 and 76.
Three-Phase Motors/Step-Direction Motors Control Lines
(P-rt/STEP, PTE/DIRC, PH3): These three control lines
provide either of the following outputs: successive
three-phase pulses (active high PH3 signal and active
low W and P-HT? signals) over the lines.ft_srthree-phase
stepping motors; or a level over the PH2/DlRC line
(high level for stepping in and low level for stepping out)
and 4 microsecond high-level pulses over the TH-I/STE?
line to determine the direction and stepping rate for
step-direction motors. For direction control of three-
phase motors, the stepping sequence is 1-2-3-1 when
stepping in and 1-3-2 when stepping out. The particular
motor interface selected is determined by the hardwiring
of the Tm input. The FiTi/STEP output is made active
low after a master reset.
Head Load (HLD): High-level output that controls the
loading of the Read/Write head against the recording
medium (diskette). A Read or Write operation does not
occur until a high-level HLT input is sampled by the
lNS1771-1, The HLD becomes active at the beginning of
a Read, Write (E flag is sethigh) or Verify operation, or
a Seek or Step Operation with the H flag set high; it
remains active until the third index pulse following the
last operation that used the head.
INPUT/OUTPUT SIGNALS
Data Access Lines (DAL) Bus: This TRl-STATE bus
comprises eight inverted input/output lines IDAL0-
DAL7). The bus provides bidirectional communications
between the CPU and the INS1771-1. Data, control
words and status information are transferred via the
DAL Bus.
Pin Configuration
1ltttt- 1 V 40 -- Iltm
Te-- 2 M -INtR0
rs--- 3 " --oRtl
RE - 4 37 .--DI-NT
Ao- 5 35 -..-weRT
m _-- 6 35 - W
trm - 7 " '--rii0T
Em - a 33 -WT
taa-Li--.. ' " - REAOY
DAL3-- lo 31 ---m)
m_ It |N81771-1 " _WG
Tii-rs-- 12 " - mu
iTECii 11 " '--tiro
Iya-Li-l " 27 - Fnomn
mi/srrr'e 15 " - FIJELK
[Ctg/0iRc-- 16 25 - 71E
PHST 17 " - CLK
atM--- 13 " - HLT
-im,- MI 22 -fiiFT
V53 20 21 -vix
|NS1771-1 Commands
The lNS1771-1 accepts and executes the eleven com-
mands listed and summarized in table 1. Flags associated
with these commands are summarized in table 2. With
the exception of the Force Interrupt command, a
command word should be loaded into the internal
Command Register only when bit 0 (Busy) of the Status
Register is inactive (low). Whenever a command is being
executed, the Busy status bit is set high. When a com-
mand is completed or an error condition exists, an
interrupt is generated and the Busy status bit is reset
low. The Status Register indicates whether a completed
command encountered an error or was fault free.
As indicated in table l, the eleven commands accepted
and executed by the lNSl771-1 are divided into four
types. The following paragraphs describe the eleven
commands under these four divisions.
TYPE I COMMANDS
Type l Commands are basically head positioning com-
mands and include the Restore, Seek, Step, Step-In, and
Step-Out commands. Each of the Type I Commands
contains a rate (r1r0) field (hits 0 and 1) that determines
the stepping motor rate as defined in the table below:
The Type I Commands contain a head load (h) flag
(bit 3) that determines whether or not the head is to be
loaded at the beginning of the command. If h = 1, the
head is loaded at the beginning of the command (HLD
output made active high). If h = O, the HLD output is
made inactive low. Once the head is loaded (HLD is
active),the head will remain engaged until the INSI 771-1
receives a command that specifically disengages the head.
If the INS1771-1 does not receive any commands after
two revolutions of the disk, the head will be disengaged
(HLD made inactive). The Head Load Timing (HLT)
input is only sampled after a 10 millisecond delay, when
actual reading or writing on the diskette is to occur.
Note that a verification, described below, requires
reading off the diskette.
The Type I Commands also contain a verification (Vl
flag (bit 2) that determines whether or not verification is
to take place on the last track. lf V = 0, no verification is
performed. If V = l, a verification is performed.
During verification, the head is loaded (HLD is active)
and after an internal 10 millisecond delay, the HLT
input is sampled. When the HLT input is active (high),
CLK =/MH,
CLK =2MHz CLK=2MHZ CLK =1MHz
r1 r0 TEST =1 TEST =1 TEST = 0 TEST = 0
0 0 6 ms 12 ms N
0 0 6 ms 12 ms
1 0 10ms 20ms T400” T800”
1 I I 20 ms 40 ms
Table 1. Commands Summary
"l -coTda,-,dT-,
T 6 514 3 2 17 o
I ‘Restore 0 01010 h v r11r0
I Seek 0 O 1 0 l 1 h V r1 r0
I (Step 0 031iu hls/ r1 r0
l [Stepin o 1!01u hlv’q r0
I (tepOut 0 1111U1h‘Vir1 r0
ll 2C,ydCCC,"1 1 0 [ 0 m l b E 0 0
II Write Command! 1 O I 1 1 m b ( E a1 ao
Ill ReadAddress 1 1 " I 0 l 0 11 0 0
lil .ReadTrack 1 ,1.01011 0 ii
III Write Track 1 i I 1 1 I 0 1 O 0
IV Forcelnterrupt 1 L 10 1 ‘13 lng-l Io
Table 2. Command Flags Summary
h = Head Load flag (bit 3 of Type "
= 1, Load head at beginning
h = 0, Do not load head at beginning
V = Verify flag (bit 2 of Type "
V = 1, Verify on last track
V = 0, No verify
mm = Stepping Motor Rate (bits l- O of Type "
mm = 00, 6 ms between steps
mm = 01, 6 ms between steps
r1r0 = 10, 10 ms between steps
r1r0 = 11, 20 ms between steps
u = Update flag (bit 4 of Type I)
u = 1, Update Track Register
u = 0, No update
m = Multiple Record flag (bit 4 of Type II)
m = 0, Single Record
m = l, Multiple Records
T b = Block Length flag (bit 3 of Type H)
b = 1, IBM format (128 to 1024 bytes)
b = 0, Non-IBM format (16 to 4096 bytes)
E " Enable HLD &10ms delay (bit 2 of Type II)
E = 1, Enable HLD, HLT &10ms delay
E = 0, Head is assumed engaged & no 10ms delay
a1ao = Data Address Mark (bits 1 - O of Type ll)
a1ao = 00, FB (Data Mark)
3130 = 01, FA (Data Mark)
a1a0 :10,F9 (Data Mark)
a1ao =11,F8 (DataMark)
T = Synchronize flag (bit 0 of Type III)
= 0, Synchronize to AM
T---- 1, Do not synchronize to AM
In = Interrupt Condition flags (bits 3 - 0 of Type IV)
10 = l, Not Ready to Ready Transition
I1 = 1, Ready to Not Ready Transition
I2 =1,|ndex Pulse
I3 = l, Every 10ms
lNS1771-1 Commands (cont.)
the first encountered ID field is read off the diskette.
The track address of the ID field is then compared to the
Track Register. If there is a match and a valid ID CRC,
the verification is complete, an interrupt is generated,
and the Busy status bit is reset. If there is not a match
and a valid ID CRC, an interrupt is generated, the Seek
Error status bit (bit 4) is set high, and the Busy status
bit is reset low. If there is not a valid CRC, the CRC
Error status bit (bit 3) is set high, and the next encoun-
tered ID field is read off the diskette for verification. If
an ID field with a valid CRC cannot be found after two
revolutions of the diskette, the |NS1771-1 terminates
the operation and sends an interrupt (INTRO) signal to
the CPU.
The Step, Step-in and Step-Out commands contain an
update (u) flag (bit 4). When u = 1, the Track Register
is updated by one for each step. When u = 0, the Track
Register is not updated.
|NS1771-1 Commands (cont.)
Restore (Seek Track 0): Upon receipt of this command,
the Track 00 (TROO) input is sampled. If TROO is active
low (indicating the Read/Write head is positioned over
track 0), the Track Register is loaded with zeros and an
interrupt is generated. it TROO is not active low, stepping
pulses at a rate specified by the r1r0 field (bits 0 and 1)
are issued until the TROO input is active low. At this
time, the Track Register is loaded with zeros and an
interrupt is generated. If the TROO input does not go
active low after 255 stepping pulses, the INS1771-1
gives up and interrupts with the Seek Error status bit
set. Note that the Restore command is executed when
the M_R input goes from an active (low) to an inactive
(high) state. A verification operation takes place if the
V flag (bit 2) is set. The setting of the h flag (bit 3)
allows the head to be loaded at the start of the command.
Seek: This command assumes that the Track Register
contains the track number of the current position of the
ReadN/rite head and that the Data Register contains the
desired track number. The INS1771-t will update the
Track Register and issue stepping pulses in the appro-
priate direction until the contents of the Track Register
are equal to the contents of the Data Register. A verifir
cation operation takes place if the V flag (bit 2) is set.
The setting of the h fiag (bit 3) allows the head to be
loaded at the start of the command. An interrupt is
generated at the completion of the command.
Step: Upon receipt of this command, the INS1771-1
issues one stepping pulse to the floppy disk drive. The
stepping motor direction is the same as in the previous
step command. After a delay determined by the r1r0
field (bits 0 and ll, a verification takes place if the V
flag (bit 2) is set. If the u flag (bit 4) is set, the Track
Register is updated. The setting of the h flag (bit 3)
allows the head to be loaded at the start of the com-
mand. An interrupt is generated at the completion of the
command.
Step-ln: Upon receipt of this command, the INS1771-1
issues one stepping pulse in the direction towards track
76. If the u flag (bit 4) is set, the Track Register is
decremented by one, After a delay determined by the
r1ro field (bits 0 and 1), a verification takes place if the
V flag (bit 2) is set. The setting of the h flag (bit 3)
allows the head to be loaded at the start of the com-
mand. An interrupt is generated at the completion of the
command.
Step-Out: Upon receipt of this command, the INS1771-1
issues one stepping pulse in the direction towards track
0. If the u flag (bit 4) is set, the Track Register is decre-
mented by one. After a delay determined by the r1r0
field (bits 0 and 1), a verification takes place if the V
flag (bit 2) is on. The setting of the h flag (bit 3) aliows
the head to be loaded at the start of the command. An
interrupt is generated at the completion of the command.
TYPE I I COMMAN DS
The Type II Commands include the Read sector(s) and
Write sector(s) commands. Prior to loading the Type II
Commands into the Command Register, the computer
must load the Sector Register with the desired sector
number. Upon receipt of the Type II Commands, the
Busy status bit is set. If the E flag (bit 2) = l (this is the
normal case), HLD is made active and HLT is sampled
after an internal 10 millisecond delay, If the E flag = O,
the head is assumed engaged and there is no internal
10 millisecond delay.
When an ID field (see figure ll is located on the diskette,
the INS1771-1 compares the Track Number of the ID
field with the Track Register. if there is not a match, the
next encountered ID field is read and a comparison is
made. If there is a match, the sector number of the ID
field is then compared with the Sector Register. If there
is not a match, the next encountered ID field is read and
a comparison is made. If there is a match, the CRC field
is read. (The polynomial for the CRC is G(x) = x16 +
x12 + x5 + 1. The CRC includes all the information
starting with the address mark and up to the CRC
characters.) if there is a CRC error,1he CRC Error status
bit is set and the next ID field is read off the diskette
and comparisons are made. If the CRC is correct, the
data field is located and will be either written or read,
depending upon command. The INS1771-1 must find an
ID field with a valid track number, sector number, and
CRC within two revolutions of the diskette; otherwise,
the Record Not Found status bit (bit 4) is set and the
command is terminated with an interrupt.
SECTOR
IO TRACK
titu'3 AM NUMBER ZER0S NUMBER
SECTOR CRC ' CHE DATA CHI: CRC
LENGTH 1 l GAP2 DATA 1 2 GAPS
m m tll I mi I (1) (128) iii i2) (33)
I I 'd',U/C-uu
(N0.0FBYTES)-- in) m Ill m (1)
V-'----'-"----, IDFIELD
IDAM =|D ADDRESS MARK;DATA= (FE),CLK:(C7|
DATA AM r, DATA ADDRESS MARK, DATA = (F3, Fil. FA. OR F8), CLK r. (Cr)
Figure 1. IBM 3740 ID Field and Data Field Formats
lNS1771-1 Commands (cont.)
Each of the Type II Commands contains a b flag (bit 3),
which in conjunction with the sector length field
contents of the ID, determines the length (number of
characters) of the data field. For IBM 3740 compatibility,
the b flag (bit 3) should equal 1. The numbers of bytes
in the data field (sector) is then 128 x 2n where n = 0,
1, 2, or 3.
For b = 1 :
Sector Length Number of Bytes
Field (hex) in Sector (decimal)
00 128
O1 256
02 512
03 1024
When the b flag (bit 3) equals zero, the sector length
field (n) multiplied by 16 determines the number of
bytes in the sector or data field as shown below:
For b = 0:
Sector Length Number of Bytes
Field (hex) in Sector (decimal)
FF 4080
00 4096
Each of the Type II Commands also contains an m flag
(bit 4) that determines whether multiple records (sectors)
are to be read or written, depending upon the command.
If m = O, a single sector is read or written and an inter-
rupt is generated at the completion of the command. If
m = l, multiple records are read or written with the
Sector Register internally updated so that an address
verification can occur on the nextrecord.The INS1771-1
continues to read or write multiple records and update
the Sector Register until the Sector Register exceeds the
number of sectors on the track or until the Force
Interrupt command is loaded into the Command Register.
When either of these occurs, the command is terminated
and an interrupt is generated.
Read Command: Upon receipt of this command, the
Read/Write head is loaded and the Busy status bit is set.
Then, when an ID field is encountered that has the
correct track number, correct sector number, and
correct CRC, the data field is inputted to the computer.
The Data Address Mark of the data field must be found
within 28 bytes of the correct ID field. If not, the
Record Not Found status bit is set and the operation is
terminated. When the first character or byte of the data
field has been shifted through the Data Shift Register,
it is transferred to the Data Register and a Data Request
(DRO) output is generated. When the next byte is
loaded into the Data Shift Register, it is transferred to
the Data Register and another DRG output is generated,
provided that the CPU has previously read the Data
Register. If one or more characters are lost, the Lost
Data status bit is set. This sequence continues until the
data field has been inputted to the computer. If there is
a CRC error in the data field, the CRC Error status bit is
set, and the command is terminated (even if it is a
multiple record command). At the end of the operation,
the type of Data Address Mark encountered in the data
field is recorded in the Status Register (bits 5 and 6) as
shown below:
Status Bit 5 Status Bit 6 Data AM (hex)
O 0 FB
0 1 FA
1 0 F9
1 1 F8
Write Command: Upon receipt of this command, the
Read/Write head is loaded (HLD active) and the Busy
status bit is set. When an ID field is encountered that has
the correct track number, correct sector number, and
correct CRC, a DRQ output is generated. The INS1771-1
counts off 11 bytes from the CRC field and the Write
Gate (WG) output is made active if the DRO is serviced
(i.e., the Data Register has been loaded by the computer).
If DRO has not been serviced, the command is termim
ated and the Lost Data status bit is set. If the DRQ has
been serviced, the WG is made active and six bytes of all
Zero levels are then written on the diskette. At this
time, the Data Address Mark is then written on the
diskette, as determined by the 3130 field (bits 0 and 1)
of the command as shown below:
a1 a0 Data Mark (hex) Clock Mark (hex)
0 0 FB C7
0 1 FA C7
1 0 F9 C7
1 1 F8 C7
The |NS1771-1 then writes the data field by generating
DRO outputs to the computer. If the DEC is not
serviced in time, the Lost Data status bit is set and a
byte of zeros is written on the diskette. The command is
not terminated. After the last data byte has been written
on the diskette, the two-byte CRC is computed internally
and written on the diskette followed by one byte of all
One levels. WG is then made inactive.
TYPE III COMMANDS
Read Address: Upon receipt of this command, the head
is loaded and the Busy status bit is set. The next encoun-
tered ID field is then read in off the diskette, and the
six data bytes of the ID field are assembled and trans-
ferred to the Data Register, and a DRQ output is gener-
ated for each byte. (The six bytes of the ID field are
shown in figure 1.)
Although the CRC characters are inputted to the com-
puter, the |NS1771-1 checks for validity and the CRC
Error status bit is set if there is a CRC error. The Sector
Address of the ID field is written into the Sector
Register. At the end of the operation, an interrupt is
generated and the Busy status bit is reset.
|NS1771-1 Commands (cont.)
Read Track: Upon receipt of this command, the head is
loaded and the Busy status bit is set. Reading starts with
the leading edge of the first encountered index mark and
continues until the next index pulse. As each byte is
assembled, it is transferred to the Data Register and the
Data Request (DRQ) output is generated for each byte.
No CRC checking is performed. Gaps are included in the
input data stream. If the s flag (bit 0) of the command
is a low, the accumulation of bytes is synchronized to
each Address Mark encountered. Upon completion of
the command, the interrupt is activated.
The |NS1771-1 handles single density frequency modu-
lated (FM) data. Each data cell is defined by clock
pulses. A pulse recorded between clock pulses indicates
the presence of a logic 1 bit; the absence of this puise
is interpreted as a logic 0 bit. The Address Marks for
Index, ID, and Data are identified by a particular pattern
not repeated in the remainder of the ID field or Data
field. This is accomplished by reading patterns that are
recorded with missing clock bits (logic O) as shown
below:
For initialization:
Write 2 CHC Characters Data 1 1 1 1 0 1 1 1 = F7
Clock1 1 1 1 1 1 1 1 = FF
Index Address Mark Data 1 1 1 1 1 1 0 0 = FC
Clock1 1 0 1 O 1 1 1 = D7
ID Address Mark Data 1 1 1 1 1 1 1 0 = FE
Clock1 1 0 o 0 1 1 1 = C7
Data11111011--F9-Fi?
Clock11000111-C7
Data Address Mark
Deleted Data 1 1 1 1 1 t) 0 o-- F8
Data Address Mark Clock1 1 O o 0 1 1 1 = C7
Spare Data 11111101=FD
Clock (user designated)
These patterns are used as synchronization codes by the
INS1771-1 when reading data and are recorded by the
formatting command (Write Track) when the lNS1771-1
is presented with data F7 through FE.
Write Track: Upon receipt of this command, the head is
loaded and the Busy status bit is set. Writing starts with
the leading edge of the first encountered index pulse
and continues until the next index pulse. at which time
the interrupt is activated. The Data Request output is
activated immediately upon receiving the command and
writing does not start until after the first byte has been
loaded into the Data Register. If the Data Register has
not been loaded by the second index pulse, the operation
is terminated. This sets the Not Busy and Lost Data
status bits, and activates the interrupt. If a byte is not
present in the Data Register when needed, a byte of
zeros is substituted. Address Marks and CRC characters
are written on the diskette by detecting certain data
byte patterns in the outgoing data stream as shown
above. The CRC generator is initialized to all Ones when
any data byte from F8 to FE is about to be transferred
from the Data Register to the Data Shift Register.
The Write Track command does not execute if the DI NT
input is grounded. Instead, the Write Protect status bit
is set and the interrupt is activated. One F7 pattern in
the Data Register generates 2 CRC characters.
TYPE IV COMMANDS
Force Interrupt: This command can be loaded into the
Command Register at any time. If there is a current
command under execution (Busy status bit is set), the
command is terminated and an interrupt is generated
when the condition specified in the m through I3 field
(bits 0 through 3) is detected. More than one condition
may be specified. The interrupt conditions are indicated
below:
lo = Not Ready-to-Ready Transition
13-- Interrupt occurs within 1 to 10 milliseconds
and every 10 milliseconds thereafter.
If IO through I3 = 0, no interrupt is generated;
however, the current command is terminated and
the Busy status bit is reset.
Ready-to-Ready Transition
Every Index Pulse
|NS1771-1 Status Register
An 8-bit register is provided in the INS1771-1 to hold
device status information. This Status information varies
according to the type of command executed as shown
in table 3. The contents of the Status Register, which
can be read into the DAL Bus by a Read operation,
are described below.
Bit 0: When high (set), indicates that a command is
under execution. When low (reset), indicates that no
command is under execution.
Bit1: For Type I Comrgands, this bit is the comple-
ment of the Index Pulse HP) input. When set, it indicates
that an index mark has been detected on the diskette.
For Types II and III Commands, this bit is a copy of the
Data Request (DRG) output. When set, it indicates that
the Data Register is full during a Read operation or that
the Data Register is empty during a Write operation. Bit
1 is reset to zero when updated.
Bit 2: For Type I Commands, this bit is the complement
of the Track 00 (TROO) input. When set, it indicates
that the Read/Write head is positioned over track 0.
For Types II and Ill Commands, this bit is set to indicate
that the computer did not respond to the DRO output
from the |NS1771-1 in one byte time. Bit 2 is reset to
zero when updated.
Bit 3: For Type I Commands, this bit is set when one or
more CRC errors were encountered on an unsuccessful
Track Verification operation. Bit 3 is reset to zero when
updated.
For Type II and Ill Commands, bit 3 is set when an
error is found in one or more ID fields, while bit 4 is set.
Bit 3 is reset low when updated.
Bit 4: For Type I Commands, this bit is set to indicate
that the desired track was not verified. Bit 4 is reset
low when updated.
For Type II and III Commands, bit 4 is set to indicate
that the desired track and sector were not found. Bit 4 is
reset low when updated.
Bit 5: For Type I Commands, this bit is set to indicate
that the Read/Write head is loaded and engaged. Bit 5
INS1771-1 Commands (cont.)
is the logical AND of the Head Load (HLD) output
and the Head Load Timing-(HLT) input.
For Type II and III Commands, bit 5 indicates the
following: the LSB of the recoritype code from the
data field address mark during execution of a Read
Command; and a write fault during execution of a Write
or Write Track Command. Bit 5 is reset low when
updated.
Bit 6: For Type I Commands, this bit is the complement
of the Write Protect (WRPT) input, When set, it indicates
that the write protect is activated.
For Type II and Ill Commands, bit 6 indicates the
following: the MSB of the record-type code from the
data field address mark during execution of a Read
Command; and a write fault during execution of a Write
or Write Track command. Bit 6 is reset low when up-
dated.
Bit 7: When set, indicates that the floppy disk drive is
not ready. When reset, indicates that the drive is ready.
Bit 7 is the complement of the Ready input and is
logically ORed with the Master Reset (W) input, The
Types II and Ill Commands are not executed unless the
floppy disk drive is ready,
Table 3. Status Register Summary
Commands
Bit All Type l i" Read T Read Write
Commands Address Read Track Write Track
S7 Not Ready I Not Ready Not Ready Not Ready Not Ready Not Ready
S6 Write Protect l 0 Record Type 0 Write Protect Write Protect
SS 1 Head Engaged I 0 ( Record Type 0 Write Fault Write Fault
S4 , Seek Error ID Not Found 1 Record Not Found 0 Record Not Found , 0
S3 _ CRC Error CRC Error CRC Error 0 CRC Error , 0
S2 Track 0 Lost Data Lost Data Lost Data Lost Data Lost Data
Sl Index DRO DRO DRO DRO DRO
SO : Busy Busy Busy Busy Busy " Busy
Programming Examples
Some examples of the software control of the INS1 771-1
are shown in flowchart form.The first example (figure 2)
shows the writing of information onto a particular track
and sector. The second example (figure 3) shows acces-
sing of information from successive sectors. The third
example (figure 4) shows how information may be
sought by using Track 00 as a table of contents.
INS1771-1 Operation
The following describes the operation of the |NSI771-1.
Use the block diagram on page 5, as necessary, to follow
these descriptions.
ItilS1771-1 PROCESSOR INTERFACE
All commands, status and data are transferred over the
TRl-STATE bidirectional DAL (Data Access Lines) Bus.
The 8 lines of the DAL Bus (DALO - DAL?) present an
open circuit to the comman processor peripheral bus
until activate_d by the low~levei c7; (Chip Select) signal.
An active CS combined with a low-level R-E (Read
Enable) set§_the DAL Bus into the transmitter mode.
while the CS combined with a low-Ievel WE (Write
Enable) sets the DAL Bus in the receiver mode.
When transfer of data with the INS1771-1 is required
It the host processor, the device address is decoded and
CS is made low. The least signific_ant address bits A1 and
A0, combined with the signals RE during a Read opera-
tion or m during a Write operation, are interpreted as
selecting the following registers:
A1 A0 Read (R-E) Write (m)
0 0 Status Register Command Register
0 1 Track Register Track Register
1 0 Sector Register Sector Register
1 1 Data Register Data Register
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the INS1771-1
and the processor, the Data Request (DRQ) output is
used in Data Transfer control. This signal also appears as
status bit 1 during Read and Write operations.
On Disk Read operations, the Data Request (DRO)
output is activated (set high) when an assembled serial
input byte IS transferred in parallel to the Data Ftegister.
This bit is cleared when the Data Register is read by the
processor. if the Data Register is read after one or more
REPEAT SEEK
OPERATION DR
DO DIAGNOSTIC
lNS1771-1 Programming Examples (cont.)
SEND DESIRED
TRACK N0.T0
TRACK REG =
1010 0011
SEND DESIRED
SECTOR N0.T0
SECTOR REG =
SEND SEEK CMO
WITH VERIFY T0
CMO REG = 00011101
lNTRIl
READ STATUS
REGISTER 8
MASK MII 1100
THERE AN
ERROR?
THACK=A3
AODR=01
SECTDR=15
Anun=1a
HEAD LOAD ACTIVATED
VERIFY REQUESTS
Ems STEP RATE
Mort = 00
Annazou
'TE--t
I HEAD IS ASSUMED LOADED FROM
SEND WRITE
COMMAND
= 1010 0000
+ INTRO
READ STATUS
REGISTER
PERFORM ERROR
DIAGNOSTICS
PERFORM ERROR
DIAGNOSTICS
SEEK IlPERATl0N.WRITE SINGLE
SECTOR, IBM SECTOR FORMAT
(128 BYTES).
DATA ADDRESS MARK = FB
ADDR = 00,W_E = 0
READ THE
BYTE FROM
MEMORY AND
INCREMENT ADDH
ADDH=11
SEND THE BYTE W-E--,
T0 TH E DATA
REGISTER NUI
THERE AN
ERROR?
Figure 2. Writing Data
READ THE
STATUS REGISTER
& MASK = 0001 1000
OPERATION
COMPL ETE
lNS1771-1 Programming Examples (cont.)
ASSUMES:
- TRACK IS LOCATED
- DESIRED SECTOR IS lOADEO
READ STATUS INTRO sewn READ cum ENABLE HEAD LOAD AND
REGISTER & l- TO THE CMI? REG 'l1l'lll'htPiTflll1,
MASK mm 1000 40011100 (123 BYTES/SECTOR)
------9 DRE]
READ DATA FROM -
DATA REGISTER ADDR =11,ne = a
STORE IN
MEMORY AND
men ADDR NOTE:
NO, OF mas TRANSFERRED
I SHOULD encompnss TOTAL
SECTORS TO ALLOW VALID
cnc CHECKS.
COMPLETE?
READ STATUS -
REG & MASK C" - tlo
FOR ERRORS RE--il
' mm 0000
REREAD on IS
PERFORM ERROR THERE AN
DIAGNOSTICS ERROR?
SEND FORCE
IN;ERRUPT C3“) AOOR = 00
0 cm RE - =
=nu1 uuno WE i)
l CONTINUE
Figure 3. Reading Successive Sectors of Data
lNS1771-1 Programming Examples (cont.)
oo DIAGNOSTIC
SUCH M READ
ADDRESS CMO
SEND RESTORE
CMD T0 CMD REG
= 00001101
l INTRO
READ STATUS
REG AND MASK
= 0001 1000
THERE AN
ERROR?
ADDR = In,TeT = tl
ENABLE HEAD LOAD AND VERIFY
ENABLE EmsSTEP RATE
ADDR=00,FE= ll
T"-""'''"
READ MU LTIPLE
SECTORS 8 - 26
COMPARE LABEL
AND DERIVE
TRACK AND SECTOR
LOCATION
PERFORM LOCATE
DATA AND
READ IN
ASSEM8LEO DATA
j COMPLETE
Figure 4. Using Track 00 as Table of Contents
characters are lost, by having new data transferred into
the register prior to processor readout, the Lost Data bit
is set in the Status Register. The Read operation con-
tinues until the end of sector is reached.
On Disk Write operations, the Data Request output is
activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data byte.
It is reset when the Data Register is loaded with new
data by the processor. If new data is not loaded at the
time the next serial byte is required by the floppy
disk drive, a byte of zeroes is written on the diskette and
the Lost Data bit is set in the Status Register.
The Lost Data bit and certain other bits in the Status
Register will activate the Interrupt Request (INTRO)
output. The interrupt line is also activated with normal
completion or abnormal termination of all controller
operations. The INTRO signal remains active until reset
by reading the Status Register to the processor or by the
loading of the Command Register. In addition, the
INTRO output is generated if a Force Interrupt com-
mand condition is met.
|NS1771-1 FLOPPY DISK DRIVE INTERFACE
The INS1771-1 floppy disk drive interface consists of
head positioning controls, write gate controls, and data
transfers. A 2.0 MHz t 1% square wave clock is required
at the CLK input for internal control timing. (A 1.0 MHz
clock is required for a miniature floppy disk.)
Head Positioning
Four commands cause positioning of the Read/Write
head (see INS1771-1 Commands section). The period of
each positioning step is specified by the r field in bits 1
and 0 of the command word. After the last directional
step, an additional 10 milliseconds of head settling time
takes place. The four programmable stepping rates
(mm) are tabulated under the Type I Commands des-
cription.
The r1r0 rates can be applied to a three-phase motor or
a step-direction motor through the device interface.
When the 5p7i input is connected to ground the device
operates with a three-phase motor control interface,
with one active signal per phase on the three output
signals (5171, W and PH3). The stepping sequence
is 1-2-3-1 when stepping in and 1-3-2-1 when stepping
out. Phase 1 is active low after Master Reset.
The Step-Direction Motor Control interface is activated
by leaving input TPN open or connecting it to +5 Volts.
The phase 1 pin (pm) becomes a step pulse of 4 micro-
seconds width. The phase 2 pin FAT?) becomes a direc-
tion control, with a high voltage on this pin indicating
a Step In, and a low voltage indicating a Step Out. The
Direction output is valid a minimum of 24 microseconds
prior to the activation of the step pulse.
When a Seek, Step or Restore command is executed,
an optional verification of Read/Write head position can
be performed by setting bit 2 in the command word to
a logic 1. The verification operation begins at the end of
the 10 millisecond settling time after the head is loaded
against the medium. The track number from the first
encountered ID Field is compared against the contents
of the Track Register. If the track numbers compare
and the ID Field Cyclic Redundancy Check (CRC) is
correct, the verify operation is complete. If track com-
parison is not made but the CRC checks, an interrupt is
generated, the Seek Error status bit (bit 4) is set, and the
Busy status bit is preset. if there is no track comparison
nor a valid CRC, a step is made in the same direction as
specified and the verify operation is repeated. The
additional stepping can be repeated twice to account fo,
two defective tracks. If no verification is received at
this point, the Seek Error (bit 4) is set in the Status
Register.
The Head Load (HDL) output controls the movement
of the Read/Write head against the diskette for data
recording or retrieval. It is activated at the beginning of
a Read, Write (E flag on) or Verify operation, or aSeek
or Step operation with the head load bit (h) a logic high; it
remains activated until the third index pulse following
the last operation which uses the Read/Write head.
Reading or Writing does not occur until a minimum of
10 milliseconds after the HDL signal is made active. If
executing the Type II Commands with the E flag off,
there is no 10 millisecond delay and the head is assumed
to be engaged. The delay is determined by sampling of
the Head Load Timing (HLT) input every 10 milli.
seconds. A low logic state input, generated from the
Head Load output transition and delayed externally,
identifies engagement of the head against the diskette.
In the Seek and Step commands, the head is loaded at
the start of the command execution when the h bit is a
logic 1. In a verify command, the head is loaded before
stepping to the destination track on the diskette when-
ever the h bit is a logic 0.
Disk Read Operation
The 2‘0MH2 external clock provided to the device is
internally divided by 4 to form the 500 kHz clock rate
for data transfer. When reading data from a diskette, this
divider is synchronized to transitions of the Read Data
(FDDATA) input. When a transition does not occur on
the 500 kHz clock active state, the clock divider circuit
injects a clock to maintain a continuous SOOkHz data
clock. The 500KHz data clock is further divided by 2
internally to separate the clock and information bits.
The divider is phased to the information by the detec-
tion of the address mark.
In the internal data read and separation mode, the Read
Data input toggles from one state to the opposite state
for each logic 1 bit of clock or information. This signal
can be derived from the amplified, differentiated, and
sliced Read Head signal, or by the output of a flip-flop
toggling on the Read Data pulses. This input is sampled
by the 2 MHz clock to detect transitions.
The chip can also operate on externally separated data,
as supplied by methods such as phase-lock loop, one-
shots, or variable frequency oscillators. This is accom-
plished by grounding the External Data Separator
(XTDS) input. When the Read Data input makes a high-
to-low transition, the information input to the FDDATA
line is clocked into the Data Shift Register. The assem-
bled 8-bit data from the Data Shift Register are then
transferred to the Data Register.
The normal sector length for Read or Write operations
with the IBM 3740 format is 128 bytes. This format or
binary multiplex of 128 bytes will be adopted by setting
a logic 1 in bit 3 of the Read Track and Write Track
commands. Additionally, a variable sector length feature
is provided which allows an indicator recorded in the ID
Field to control the length of the sector. Variable sector
lengths can be read or written in Read or Write com-
mands respectively by setting a logic 0 in bit 0 of the
command word. The sector length indicator specifies the
number of 16-byte groups, or 16 x N, where N is equal
to 1 to 256 groups. An indicator of all zeros is inter-
preted as 256 sixteen-byte groups.
Disk Write Operation
After data is loaded from the processor into the Data
Register, and is transferred to the Data Shift Register,
data will be shifted serially through the Write Data (WD)
output. Interlaced with each bit of data is a positive
clock pulse of 0.5 microsecond duration. This signal may
be used to externally toggle a tlip-flop to control the
direction of write current flow.
INST771-1 FLOPPY DISK DRIVE INTERFACE (cont.)
When writing is to take place on the diskette, the Write
Gate (WG) output is activated, allowing current to flow
into the Read/Write head. As a precaution to erroneous
writing, the first data byte must be loaded into the Data
Register in response to a Data Request from the
INS1771-1 before the Write Gate signal can be activated.
Writing is inhibited when the Write Protect (WPHT)
input is a logic 0, in which case any Write command is
immediately terminated, an interrupt is generated, and
the Write Protect status bit is set. The Write Fault (DWI
input, when activated, signifies a writing fault condition
detected in disk drive electronics such as failure to
detect write current flow when the Write Gate (W6) is
activated. On detection of this fault, the |NS1771-1
terminates the current command and sets the Write
Fault bit (bit 5) of the Status Register. The Write Fault
(WI?) input should be made inactive when the Write
Gate (WG) output becomes inactive.
Whenever a Read or Write command is received, the
lNS1771-1 samples the Ready input. If this input is
logic 0, the command is not executed and an interruptis
generated. The Seek or Step commands are performed
regardless of the state of the Ready input.
|NS1771-1 Floppy Disk Formatter/Controller
Physical Dimensions
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_ - 1 [1.050 ih010 m.tnn-nmn 1 0.1113 0.0112 11 Iln25
- (ISM) - - L- - rrar,-,c,/'" T' m - - i
an (1.270 [1.2541 (2.540 13254) 5 _ 1 “”5,
Ceramic DuaI-In-Line Package (DI
Order Number lNS1771D-1
_ - --15? am- - _--,.-)
fa-tslab-slit-riffs])-:].]?.-,];?:-);)-'])-'])-?])-'])-'))-.])-:])-?])".-,] "I—
"l,'?] _ [h55ll anus
L 11357!) nun
PINNO IINDENT "s
LHLell_3ly_lrs_lLtJriJCelrtllLtrfLiiJlLzllLsltelLsJuJrLrlbgJ[rgJzo
“5” 107621 o.uso
06011 IHi20 (ISIS) MAX ircrip--- _ tlt30-lrtN5
-..-- - - _-.-' -
(l5MO-l5r4in i , ma l 1 (1302 um)
_I---'t - 1 1
onus nuns
0625 ‘0 m (lh229-Ir38Tl 0329
' anus 1 mm 0015 0.100 1 0018 anus (11.51181
-- - - - -1 - .- _ - -. 7 7,1- - Ir125 MIN
[15n75'u'5351 11905 0331) 125411) (11.457 noun W)
n.3s1 ma MIN
Plastic Dual-In-Line Package (N)
Order Number INS1771N»1
Manufactured under gne or more or 'he ‘D‘WWW U5 ga'ents 3033261 3189758. 3231797. 3303356, 3317671. 33330711 31810t'l. 34054?, M210?5, 1426421 3440498, 3518750 35195911 3551431, 3560765
3563218 1571530 15756013579059 15930613597510 36074691 3617859 35313121 3633051, 3638131 35480V.. 36515613693358
Naiional Semiconductor Corporation
290059rn1conduclor Dom Santa Clara,Gahtornitt 95051, (403)737-5000/1wx (910) 339-9240
National Semiconductor GmbH
808 Fu.rstent.ldbruck, Irtt1ustrtestrttsse to, West Germany, Tale. (03141) 1371/1919: 05-27649
National Semiconductor (UK) Ltd.
Lavkhald Industvial Eshste, Gloenock. Scotland, Tole. (04751 33251/Telex 778-632
Nmnnal does nat mum any responmbllwy for use at any wcmuy dumbed. no Clll‘ull patent Iirtrtcts are Imphed, and National resevves the tight. at any IIITIE without notice, to change sand circuitry.
'1’" .
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
INS1771D-1 - product/ins1771d-1?HQS=TI-nu|I-nu|I-dscataIog-df-pf-null-wwe
INS1771N-1 - product/ins1771n-1?HQS=T|-nu|I-nu|I-dscatalog-df—pf—null-wwe
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