HYB25D256160BT-5 ,DDR SDRAM Components HYB25D256[800/160]BT(L)-[5/5A]256MBit Double Data Rata SDRAMPreliminary DDR400 Data Sheet Addendum ..
HYB25D256160BT-6 ,DDR SDRAM Components HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. BData Sheet Jan. 2003, V ..
HYB25D256160BT-7 ,DDR SDRAM Components HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. BData Sheet Jan. 2003, V ..
HYB25D256160CC-6 ,DDR SDRAM ComponentsData Sheet, Rev. 1.11, Feb. 2004HYB25D256[40/80/16]0CE(L)HYB25D256[40/80/16]0C[C/F] 256 Mbit Double ..
HYB25D256160CE-5 ,DDR SDRAM ComponentsData Sheet, Rev. 1.11, Feb. 2004HYB25D256[40/80/16]0CE(L)HYB25D256[40/80/16]0C[C/F] 256 Mbit Double ..
HYB25D256160CE-6 ,DDR SDRAM ComponentsData Sheet, Rev. 1.11, Feb. 2004HYB25D256[40/80/16]0CE(L)HYB25D256[40/80/16]0C[C/F] 256 Mbit Double ..
ICS9DB306BLLFT , PCI Express, Jitter Attenuator
ICS9DB306BLLFT , PCI Express, Jitter Attenuator
ICS9DB401CFLFT , Four Output Differential Buffer for PCI Express
ICS9DB401CFLFT , Four Output Differential Buffer for PCI Express
ICS9DB801CFLFT , Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
HYB25D256160BT-5
DDR SDRAM Components
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.92003-01-10, V0.9
FeaturesDouble data rate architecture: two data transfers
per clock cycleBidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiverDQS is edge-aligned with data for reads and is
center-aligned with data for writesDifferential clock inputs (CK and CK)Four internal banks for concurrent operationData mask (DM) for write dataDLL aligns DQ and DQS transitions with CK
transitionsCommands entered on each positive CK edge;
data and data mask referenced to both edges of
DQSBurst Lengths: 2, 4, or 8CAS Latency: (1.5), 2, 2.5, (3)Auto Precharge option for each burst accessAuto Refresh and Self Refresh Modes
•7.8�s Maximum Average Periodic Refresh
Interval (8k refresh)2.5V (SSTL_2 compatible) I/ODDQ = 2.6V ± 0.1V / VDD = 2.6V ± 0.1VTSOP66 package
DescriptionThe 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate archi-
tecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 256Mb DDR SDRAM effectively consists of a sin-
gle 2n-bit wide, one clock cycle data transfer at the inter-
nal DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
or Write command. The address bits registered coincident
with the Active command are used to select the bank and
row to be accessed. The address bits registered coinci-
dent with the Read or Write command are used to select
the bank and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Pre-
charge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank archi-
tecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-sav-
ing power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note: The functionality described and the timing specifi-cations included in this data sheet are for the DLL Enabled
mode of operation.
CAS Latency and Clock Frequency
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Ordering Informationa. HYB: designator for memory components
25D: DDR-I SDRAMs at Vddq=2.5V
256: 256Mb density
400/800/160: Product variations x4, x8 and x16
B: Die revision B
C/T: Package type FBGA and TSOP
L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents
-5: speed grade - see table
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Pin Configuration (TSOP66)
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Input/Output Functional Description
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Block Diagram (32Mb x 8)
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Block Diagram (16Mb x 16)
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Functional DescriptionThe 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456
bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-
data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a
single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide,
one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis-
tration of an Active command, which is then followed by a Read or Write command. The address bits regis-
tered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
InitializationDDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:DD and VDDQ are driven from a single power converter output ANDTT meets the specification ANDREF tracks VDDQ/2
The following relationship must be followed:DDQ is driven after or with VDD such that VDDQ < VDD + 0.3 VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a
read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200�s delay prior to applying an executable command.
Once the 200�s delay has been satisfied, a Deselect or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operat-
ing parameters. 200 clock cycles are required between the DLL reset and any executable command. During
the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock
cycles, a Precharge ALL command should be applied, placing the device in the “all banks idle” state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters
without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal
operation.
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Register Definition
Mode RegisterThe Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Reg-
ister is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored
information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-
tion.
Burst LengthRead and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.
The burst length determines the maximum number of column locations that can be accessed for a given
Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block
if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai
when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. The programmed burst length applies to both Read
and Write bursts.
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Mode Register Operation
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Notes: For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the
block.For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within
the block.For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access
within the block.Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
Burst TypeAccesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as
the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown in Burst Definition on page 10.
Read LatencyThe Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command
and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS
latency of 1.5 is an optional feature on this device.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally
coincident with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Operating ModeThe normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to
zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set com-
mand with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A
Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Required CAS Latencies
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Extended Mode RegisterThe Extended Mode Register controls functions beyond those controlled by the Mode Register; these addi-
tional functions include DLL enable/disable, and output drive strength selection (optional). These functions
are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is
programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-
tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded
when all banks are idle, and the controller must wait the specified time before initiating any subsequent oper-
ation. Violating either of these requirements result in unspecified operation.
DLL Enable/DisableThe DLL must be enabled for normal operation. DLL enable is required during power up initialization, and
upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The
DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit
of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command
can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon
exit of self refresh operation.
Output Drive StrengthThe normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during
mode register set. I-V curves for the normal and weak drive strength are included in this document.
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Extended Mode Register Definition
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Commands
CommandsDeselectThe Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM
is effectively deselected. Operations already in progress are not affected.
No Operation (NOP)The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register SetThe mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Reg-
ister Definition section. The Mode Register Set command can only be issued when all banks are idle and no
bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.
ActiveThe Active command is used to open (or activate) a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is
issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and com-
pleted before opening a different row in the same bank.
ReadThe Read command is used to initiate a burst read access to an active (open) row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don’t care] for
x16, [i = 9, j = don’t care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on
input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open
for subsequent accesses.
WriteThe Write command is used to initiate a burst write access to an active (open) row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8;
where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or
not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end
of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input
data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coin-
cident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the
DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that
byte/column location.
PrechargeThe Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in
all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum2003-01-10, V0.9
Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no
open row in that bank, or if the previously open row is already in the process of precharging.
Auto PrechargeAuto Precharge is a feature which performs the same individual-bank precharge functions described above,
but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in
conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the
Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Pre-
charge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command.
Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if
an explicit Precharge command was issued at the earliest possible time, as described for each burst type in
the Operation section of this data sheet.
Burst TerminateThe Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-
cently registered Read command prior to the Burst Terminate command is truncated, as shown in the Opera-
tion section of this data sheet.
Auto RefreshAuto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS
(CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a
refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t
Care” during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an aver-
age periodic interval of 7.8 �s (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system,
meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh
command is 9 * 7.8 �s (70.2�s). This maximum absolute interval is short enough to allow for DLL updates
internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC
between updates.
Self RefreshThe Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The
Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The
DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self
Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except
CKE (low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to
CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because
time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
