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HEF4046BPNXPN/a5avaiPhase-locked loop


HEF4046BP ,Phase-locked loopPin configurationHEF4046B All information provided in this document is subject to legal disclaimers ..
HEF4046BT ,Phase-locked loopINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC04 LOCMOS HE40 ..
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HEF4046BP
Phase-locked loop
1. General description
The HEF4046B is a phase-locked loop circuit that consists of a linear Voltage Controlled
Oscillator (VCO) and two different phase comparators with a common signal input
amplifier and a common comparator input. A 7 V regulator (Zener) diode is provided for
supply voltage regulation if necessary. For a functional description see Section6.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Ordering information

HEF4046B
Phase-locked loop
Rev. 5 — 18 November 2011 Product data sheet
Table 1. Ordering information
All types operate from 40 C to +85 C.
HEF4046BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4046BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4046B
Phase-locked loop
4. Functional diagram

5. Pinning information
5.1 Pinning

NXP Semiconductors HEF4046B
Phase-locked loop
5.2 Pin description

6. Functional description
6.1 VCO control

The VCO requires an external capacitor (C1) and resistor (R1) with an optional resistor
(R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO, while
resistor R2 enables the VCO to have a frequency off-set if required. The high input
impedance of the VCO simplifies the design of low-pass filters; it permits the designer a
wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a
source-follower output of the VCO input voltage is provided at SF_OUT (pin 10). If this is
used, a load resistor (RL) should be connected from SF_OUT to VSS; if unused, SF_OUT
should be left open. The VCO output (pin 4) can either be connected directly to the
comparator input COMP_IN (pin 3) or via a frequency divider. A LOW-level at the inhibit
input INH_IN (pin 5) enables the VCO and the source follower, while a HIGH-level turns
both off to minimize standby power consumption.
6.2 Phase comparators

The phase-comparator signal input SIG_IN (pin 14) can be direct-coupled, provided the
signal swing is between the standard HE4000B family input logic levels. The signal must
be capacitively coupled to the self-biasing amplifier at the signal input with smaller swings.
Phase comparator 1 is an EXCLUSIVE-OR network. The signal and comparator input
frequencies must have a 50 % duty factor to obtain the maximum lock range. The average
output voltage of the phase comparator is equal to 0.5VDD when there is no signal or noise
at the signal input. The average voltage to the VCO input VCO_IN is supplied by the
low-pass filter connected to the output of phase comparator 1. This also causes the VCO
to oscillate at the center frequency (f0). The frequency capture range (2fC) is defined as
Table 2. Pin description

PCP_OUT 1 phase comparator pulse output
PC1_OUT 2 phase comparator 1 output
COMP_IN 3 comparator input
VCO_OUT 4 VCO output
INH 5 inhibit input
C1A 6 capacitor C1 connection A
C1B 7 capacitor C1 connection B
VSS 8 ground supply voltage
VCO_IN 9 VCO input
SF_OUT 10 source-follower output 11 resistor R1 connection 12 resistor R2 connection
PC2_OUT 13 phase comparator 2 output
SIG_IN 14 signal input
ZENER 15 Zener diode input for regulated supply
VDD 16 supply voltage
NXP Semiconductors HEF4046B
Phase-locked loop

the frequency range of input signals on which the PLL will lock if it was initially out of lock.
The frequency lock range (2fL) is defined as the frequency range of input signals on which
the loop will stay locked if it was initially in lock. The capture range is smaller or equal to
the lock range.
With phase comparator 1, the range of frequencies over which the PLL can acquire lock
(capture range) depends on the low-pass filter characteristics and this range can be made
as large as the lock range. Phase comparator 1 enables the PLL system to remain in lock
in spite of high amounts of noise in the input signal. A typical behavior of this type of
phase comparator is that it may lock onto input frequencies that are close to harmonics of
the VCO center frequency. Another typical behavior is that the phase angle between the
signal and comparator input varies between 0 and 180, and is 90 at the center
frequency. Figure 3 shows the typical phase-to-output response characteristic.
Figure 4 shows the typical waveforms for a PLL with a f0 locked phase comparator 1.
NXP Semiconductors HEF4046B
Phase-locked loop

Phase comparator 2 is an edge-controlled digital memory network. It consists of four
flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers with a
common output node. When the p-type or n-type drivers are ON, they pull the output up to
VDD or down to VSS respectively. This type of phase comparator only acts on the
positive-going edges of the signals at SIG_IN and COMP_IN. Therefore, the duty factors
of these signals are not of importance.
If the signal input frequency is higher than the comparator input frequency, the p-type
output driver is maintained ON most of the time, and both the n and p-type drivers are
OFF (3-state) the remainder of the time. If the signal input frequency is lower than the
comparator input frequency, the n-type output driver is maintained ON most of the time,
and both the n and p-type drivers are OFF the remainder of the time. If the signal input
and comparator input frequencies are equal, but the signal input lags the comparator input
in phase, the n-type output driver is maintained ON for a time corresponding to the phase
difference. If the comparator input lags the signal input in phase, the p-type output driver is
maintained ON for a time corresponding to the phase difference. Subsequently, the
voltage at the capacitor of the low-pass filter connected to this phase comparator is
adjusted until the signal and comparator inputs are equal in both phase and frequency. At
this stable point, both p and n-type drivers remain OFF and thus the phase comparator
output becomes an open circuit and keeps the voltage at the capacitor of the low-pass
filter constant.
Moreover, the signal at the phase comparator pulse output (PCP_OUT) is a HIGH level,
which can be used for indicating a locked condition. Thus, for phase comparator 2, no
phase difference exists between the signal and comparator inputs over the full VCO
frequency range. Moreover, the power dissipation due to the low-pass filter is reduced
when this type of phase comparator is used, because both p and n-type output drivers are
OFF for most of the signal input cycle. It should be noted that the PLL lock range for this
type of phase comparator is equal to the capture range, independent of the low-pass filter.
With no signal present at the signal input, the VCO is adjusted to its lowest frequency for
phase comparator 2. Figure 5 shows typical waveforms for a PLL employing this type of
locked phase comparator.
NXP Semiconductors HEF4046B
Phase-locked loop

Figure 6 shows the state diagram for phase comparator 2. Each circle represents a state
of the comparator. The number at the top, inside each circle, represents the state of the
comparator, while the logic state of the signal and comparator inputs are represented by a
‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom
of each circle.
The transitions from one to another result from either a logic change at the signal input (S
representing SIG_IN) or the comparator input (C representing COMP_IN). A positive-
going and a negative-going transition are shown by an arrow pointing up or down
respectively.
The state diagram assumes, that only one transition on either the signal input or
comparator input occurs at any instant. States 3, 5, 9 and 11 represent the output condition when the p-type driver is ON. States 2, 4, 10 and 12 determine the condition when the n-type driver is ON. States 1, 6, 7 and 8 represent the condition when the output is in its high-impedance
OFF state; i.e. both p and n-type drivers are OFF, and the PCP_OUToutput is HIGH.
The condition at output PCP_OUT for all other states is LOW.
NXP Semiconductors HEF4046B
Phase-locked loop
7. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1] -750 mW
SO16 package [2] -500 mW power dissipation per output - 100 mW
Table 4. Recommended operating conditions

VDD supply voltage 3 - 15 V
as fixed oscillator only 3 - 15 V
phase-locked loop operation 5 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate for INH input
VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
NXP Semiconductors HEF4046B
Phase-locked loop
9. Static characteristics

[1] Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 open.
[2] Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 at VDD;input current pin 14 not included.
Table 5. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.
VIH HIGH-level
input voltage IO < 1 A 5V 3.5 - 3.5 - 3.5 - VV 7.0 - 7.0 - 7.0 - VV 11.0 - 11.0 - 11.0 - V
VIL LOW-level
input voltage IO < 1 A 5V - 1.5 - 1.5 - 1.5 VV - 3.0 - 3.0 - 3.0 VV - 4.0 - 4.0 - 4.0 V
VOH HIGH-level
output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level
output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level
output current
VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output
current
VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA input leakage current 15 V - 0.3 - 0.3 - 1.0 A
IOZ OFF-state
output current
output HIGH and
returned to VDD
15 V - 1.6 - 1.6 - 12.0 A
output LOW and
returned to VSS
15 V - 1.6 - 1.6 - 12.0 A
IDD supply current 5 V [1] - - 20 --- A
10 V [1] - - 300 - - - A
15 V [1] - - 750 - - - A
IO = 0A 5 V [2] - 20 - 20 - 150 A
10 V [2] - 40 - 40 - 300 A
15 V [2] - 80 - 80 - 600 A input capacitance for INH input - - - 7.5 - - pF
NXP Semiconductors HEF4046B
Phase-locked loop
10. Dynamic characteristics
Table 6. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns.
Phase comparators
input resistance SIG_IN input; at self-bias operating point 5 V - 750 - k
10 V - 220 - k
15 V - 140 - k
Vi(sens) input voltage
sensitivity
SIG_IN input A.C. coupled; peak-to-peak
values; R1= 10 k; R2= ; C1= 100 pF;
independentof the lock range
5 V - 150 - mV
10 V - 150 - mV
15 V - 200 - mV
VIL LOW-level input
voltage
SIG_IN and COMP_IN inputs, DC
coupled LOW; full temperature range
5 V --1.5 V
10 V - - 3.0 V
15 V - - 4.0 V
VIH HIGH-level input
voltage
SIG_IN and COMP_IN inputs, D.C.
coupled HIGH; full temperature range
5 V 3.5 --V
10 V 7.0 - - V
15 V 11.0 - - V
IIH HIGH-level input
current
SIG_IN input; at VDD 5 V - 7 - A
10 V - 30 - A
15 V - 70 - A
IIL LOW-level input
current
SIG_IN input; at VSS 5 V - 3- A
10 V - 18 - A
15 V - 45 - A
VCO
power dissipation f0 = 10 kHz; R1 = 1 M; R2 = ;
VCO_IN at 0.5 VDD; see Figure10to12
5 V - 150 - W
10 V - 2500 - W
15 V - 9000 - W
fmax maximum frequency VCO_IN at VDD; =10 k;R2=;C1=50pF
5 V 0.5 1.0 - MHz
10 V 1.0 2.0 - MHz
15 V 1.3 2.7 - MHz
f/T frequency variation
with temperature
no frequency offset (fmin = 0 Hz) 5 V [1] -0.22 to
0.30 Hz/C
10 V [1] -0.04 to
0.05 Hz/C
15 V [1] -0.01 to
0.05 Hz/C
with frequency offset (fmin > 0 Hz) 5 V [1]- 0 to
0.22 Hz/C
10 V [1]- 0 to
0.04 Hz/C
15 V [1]- 0 to
0.01 Hz/C
NXP Semiconductors HEF4046B
Phase-locked loop

[1] Over the recommended component range.
[2] The offset voltage is equal to the input voltage on pin VCO_IN minus the output voltage on pin SF_OUT.
11. Design information

f/f relative frequency
variation
for VCO see Figure 13 and 14
R1 > 10 k 5 V - 0.50 - %Hz
R1 > 400 k 10 V - 0.25 - %Hz
R1 = M 15 V - 0.25 - %Hz duty factor VCO _OUT output 5 V - 50 - %
10 V - 50 - %
15 V - 50 - %
Rin input resistance for pin VCO_IN 10 M
Source follower

Voffset offset voltage RL = 10 k; VCO_IN at 0.5VDD 5 V [2] -1.7 -V
10 V - 2.0 - V
15 V - 2.1 - V
RL = 50 k; VCO_IN at 0.5VDD 5 V - 1.5 - V
10 V - 1.7 - V
15 V - 1.8 - V
f/f relative frequency
variation
VCO output; RL > 50 k; see Figure13 5 V - 0.3 - %
10 V - 1.0 - %
15 V - 1.3 - %
Zener diode
working voltage IZ = 50A - -7.3 -V
Rdyn dynamic resistance For internal Zener diode; IZ = 1 mA - - 25 - 
Table 6. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns.
Table 7. Design information

VCO adjusts with no signal on SIG_IN VCO in PLL system adjusts center frequency (f0)
VCO in PLL system adjusts to
minimum frequency (fmin)
Phase angle between SIG_IN and COMP_IN 90 at center frequency (f0),
approaching 0 and 180 at the
ends of the lock range (2fL)
always 0 in lock
(positive-going edges)
Locks on harmonics of center frequency yes no
Signal input noise rejection high low
Lock frequency range (2fL) the frequency range of the input signal on which the loop will stay locked if it
was initially in lock; 2fL= full VCO frequency range = fmax fmin
Capture frequency range (2fc) the frequency range of the input signal on which the loop will lock if it was
initially out of lock
depends on low-pass
filter characteristics; 2fc < 2fL
2fc = 2fL
Center frequency (f0) the frequency of the VCO when VCO_IN at 0.5VDD
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