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HCF4724BEYSTN/a150avai8 BIT ADDRESSABLE LATCH


HCF4724BEY ,8 BIT ADDRESSABLE LATCHHCF4724B8 BIT ADDRESSABLE LATCH ■ SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT■ STORAGE REGISTER CAP ..
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HCF4724BEY
8 BIT ADDRESSABLE LATCH
1/14October 2002 SERIAL DATA INPUT - ACTIVE PARALLEL
OUTPUT STORAGE REGISTER CAPABILITY -
MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER QUIESCENT CURRENT SPECIFIED UP TO
20V STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS INPUT LEAKAGE CURRENT I = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION

HCF4724B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4724B, an 8-bit addressable latch, is a
serial-input, parallel output storage register that
can perform a variety of functions. Data is input to
a particular bit in the latch when the bit is
addressed (by means of input A0, A1, A2) and
when WRITE DISABLE is at a low level. When
WRITE DISABLE is high, data entry is inhibited;
however, all 8 outputs can be continuously read
independent of WRITE DISABLE and address
inputs. A master RESET input is available, which
resets all bits to a logic "0" level when RESET and
WRITE DISABLE are at a high level. When
RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8
demultiplexer; the bit that is addressed has an
active output which follows the data input, while all
unaddressed bits are held to a logic "0" level.
HCF4724B

8 BIT ADDRESSABLE LATCH
PIN CONNECTION
ORDER CODES
HCF4724B
2/14
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLE

D: The level at the data input ; Qi0 The level before the indicated steady state input conditions were established, (i=0, 1,...7)
HCF4724B
3/14
LOGIC DIAGRAM
TIMING CHART
HCF4724B
4/14
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF4724B
5/14
DC SPECIFICATIONS

The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
HCF4724B
6/14
DYNAMIC ELECTRICAL CHARACTERISTICS (T
amb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
HCF4724B
7/14
TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
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