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HCF40103BEY
8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
1/14September 2002 SYNCHRONOUS OR ASYNCHRONOUS
PRESET MEDIUM -SPEED OPERATION : CL =3.6MHz (Typ.) at VDD = 10V CASCADABLE QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTIONHCF40103B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40103B consists of an 8-stage synchronous
down counter with a single output that is active
when the internal count is zero. This device
contains a single 8-bit binary counter. It has
control inputs for enabling or disabling the clock,
for clearing the counter to its maximum count, and
for presetting the counter either synchronously or
asynchronously. All control inputs and the
CARRY-OUT/ZERO DETECT output are
active-low logics. In normal operation, the counter
is decremented by one count on each positive
transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/
CE) input is high. The CARRY-OUT/ZERO
DETECT (CO/ZD) output goes low when the
count reaches zero if the CI/CE input is low, and
remains low for one full clock period. When the
SYNCHRONOUS PRESET ENABLE (SPE) input
is low, data at the JAM input is clocked into the
counter on the next positive clock transition
regardless of the state of the CI/CE input. When
the ASYNCHRONOUS PRESET ENABLE (APE)
input is low, data at the JAM inputs is
asynchronously forced into the counter regardless
of the state of the SPE, CI/CE, or CLOCK inputs.
JAM inputs J0-J7 represent a single 8 bit binary
word. When the CLEAR (CLR) input is low, the
counter is asynchronously cleared to its maximum
count (25510) regardless of the state of any other
input. The precedent relationship between control
input is indicated in the truth table. If all control
HCF40103B8-STAGE PRESETTABLE SYNCHRONOUS
8 BIT BINARY DOWN COUNTERS
PIN CONNECTION
ORDER CODES
HCF40103B2/14
inputs are high at the time of zero count, the
counters will jump to the maximum count, giving a
counting sequence of 256 clock pulses long.
HCF40103B may be cascaded using the CI/CE
input and the CO/ZD output, in either a
synchronous or ripple mode.
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
FUNCTIONAL DIAGRAM
TRUTH TABLES X : Don’t Care
Clock connected to Clock input
Synchronous Operation : changes occur on negative to positive clock transitions.
HCF40103B3/14
LOGIC DIAGRAM
LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7
HCF40103B4/14
TIMING CHART
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
HCF40103B5/14
DC SPECIFICATIONS The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
