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GTLP36T612FAIN/a25avai36-Bit LVTTL/GTLP Universal Bus Transceiver
GTLP36T612FAIRCHILDN/a50avai36-Bit LVTTL/GTLP Universal Bus Transceiver


GTLP36T612 ,36-Bit LVTTL/GTLP Universal Bus TransceiverFeaturesThe GTLP36T612 is an 36-bit universal bus transceiver

GTLP36T612
36-Bit LVTTL/GTLP Universal Bus Transceiver
GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver September 2001 Revised July 2002 GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver General Description Features The GTLP36T612 is an 36-bit universal bus transceiverBidirectional interface between GTLP and LVTTL logic which provides LVTTL to GTLP signal level translation. It levels allows for transparent, latched and clocked modes of dataDesigned with edge rate control circuitry to reduce out- transfer. The device provides a high speed interface for put noise on the GTLP port cards operating at LVTTL logic levels and a backplane Partitioned as two 18-Bit transceivers with individual operating at GTLP logic levels. High speed backplane latch timing and output control operation is a direct result of GTLP’s reduced output swing V pin provides external supply reference voltage for (< 1V), reduced input threshold levels and output edge rate REF receiver threshold adjustibility control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gun-Special PVT compensation circuitry to provide consis- ning Transistor logic (GTL) JEDEC standard JESD8-3. tent performance over variations of process, supply volt- age and temperature Fairchild’s GTLP has internal edge-rate control and is Pro- cess, Voltage, and Temperature (PVT) compensated. ItsTTL compatible driver and control inputs function is similar to BTL or GTL but with different output Designed using Fairchild advanced BiCMOS technology levels and receiver thresholds. GTLP output LOW level is Bushold data inputs on A port to eliminate the need for less than 0.5V, the output HIGH is 1.5V and the receiver external pull-up resistors for unused inputs threshold is 1.0V. Power up/down and power off high impedance for live insertion Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port source/sink −24mA/+24mA B Port sink +50mA For more information see AN-5026, Using BGA Packages Ordering Code: Order Number Package Number Package Description GTLP36T612G BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 DS500590
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