GTLP16616MTD ,17-Bit TTL/GTLP Bus Transceiver with Buffered ClockFeaturesThe GTLP16616 is a 17-bit registered bus transceiver that
GTLP16616MTD-GTLP16616MTDX
17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock June 1997 Revised December 2000 GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock General Description Features The GTLP16616 is a 17-bit registered bus transceiver thatBidirectional interface between GTLP and TTL logic provides TTL to GTLP signal level translation. It allows for levels transparent, latched and clocked modes of data flow andDesigned with edge rate control circuitry to reduce provides a buffered GTLP (CLKOUT) clock output from the output noise on the GTLP port TTL CLKAB. The device provides a high speed interface V pin provides external supply reference voltage for REF between cards operating at TTL logic levels and a back- receiver threshold adjustibility plane operating at GTLP logic levels. High speed back- Special PVT compensation circuitry to provide plane operation is a direct result of GTLP’s reduced output consistent performance over variations of process, swing (<1V), reduced input threshold levels and output supply voltage and temperature edge rate control. The edge rate control minimizes bus set- tling time. GTLP is a Fairchild Semiconductor derivative ofTTL compatible driver and control inputs the Gunning Transceiver logic (GTL) JEDEC standard Designed using Fairchild advanced CMOS technology JESD8-3. Bushold data inputs on the A port eliminates the need Fairchild’s GTLP has internal edge-rate control and is pro- for external pull-up resistors on unused inputs. cess, voltage, and temperature (PVT) compensated. Its Power up/down and power off high impedance for live function is similar to BTL and GTL but with different output insertion levels and receiver threshold. GTLP output LOW level is 5 V tolerant inputs and outputs on the LVTTL ports typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.Open drain on GTLP to support wired-or connection Flow through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port source/sink −32 mA/+32 mA GTLP Buffered CLKAB signal available (CLKOUT) Ordering Code: Order Number Package Number Package Description GTLP16616MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide GTLP16616MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2000 DS500017
