GTLP16612MTDX ,CMOS 18-Bit TTL/GTLP Universal Bus TransceiverGTLP16612 18-Bit TTL/GTLP Universal Bus TransceiverMarch 1995Revised March 2001GTLP1661218-Bit TTL/ ..
GTLP16616 ,17-Bit TTL/GTLP Bus Transceiver with Buffered ClockFeaturesThe GTLP16616 is a 17-bit registered bus transceiver that
GTLP16612MEA-GTLP16612MEAX-GTLP16612MTD-GTLP16612MTDX
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver March 1995 Revised March 2001 GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver General Description Features The GTLP16612 is an 18-bit universal bus transceiverBidirectional interface between GTLP and TTL logic which provides TTL to GTLP signal level translation. The levels device is designed to provide a high speed interfaceDesigned with an edge rate control circuit to reduce between cards operating at TTL logic levels and a back- output noise on GTLP port plane operating at GTLP logic levels. High speed back- V pin provides external supply reference voltage for REF plane operation is a direct result of GTLP’s reduced output receiver threshold adjustability swing (<1V), reduced input threshold levels and output Special PVT compensation circuitry to provide edge rate control which minimizes signal settling times. consistent performance over variations of process, GTLP is a Fairchild Semiconductor derivative of the Gun- supply voltage and temperature ning Transceiver Logic (GTL) JEDEC standard JESD8-3. TTL compatible Driver and Control inputs Fairchild’s GTLP has internal edge-rate control and is Pro- cess, Voltage, and Temperature (PVT) compensated. ItsDesigned using Fairchild advanced CMOS technology function is similar to BTL or GTL but with different driver Bushold data inputs on A port to eliminate the need for output levels and receiver threshold. GTLP output low volt- external pull-up resistors for unused inputs age is typically less than 0.5V, the output high is 1.5V and Power up/down and power off high impedance for live the receiver threshold is 1.0V. insertion 5V tolerant inputs and outputs on LVTTL port Open drain on GTLP to support wired-or connection Flow-through pinout optimizes PCB layout D-type flip-flop, latch and transparent data paths A Port outputs source/sink −32 mA/+32 mA Ordering Code: Order Number Package Number Package Description GTLP16612MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide GTLP16612MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2001 DS012390
