GAL6001-30LNC ,30 ns, 150 mA, 5 V, generic array logicFeatures
Electrically erasable cell technology
- Instantly reconfigurable logic
- Instantly re ..
GAL6001-30LNC ,30 ns, 150 mA, 5 V, generic array logicBlock Diagram " GAL6001
“PUTS
2-1 1
ohnns
u-zs
OUTPUT
CLOCK
TL/L/1 0561 -1
2-217
..
GAL6002B-15LJ , High Performance E2CMOS FPLA Generic Array Logic
GAL6002B-15LJ , High Performance E2CMOS FPLA Generic Array Logic
GAL6002B-15LP , High Performance E2CMOS FPLA Generic Array Logic
GAL6002B-20LJ , High Performance E2CMOS FPLA Generic Array Logic
GS3T5-5.2 ,3 W DC-DC CONVERTER FOR ECLGS3T5-5.23 W DC-DC CONVERTER FOR ECLType V V Ioi oGS3T5-5.2 5 V 5,2 V 600 mADESCRIPTIONThe GS3T5-5. ..
GS4881-CKA , Monolithic Video Sync Separators
GS4881-CTA , Monolithic Video Sync Separators
GS4881-IKA , Monolithic Video Sync Separators
GS4882 , Video Sync Separators with 50% Sync Slicing
GS4882 , Video Sync Separators with 50% Sync Slicing
GAL6001-30LNC
30 ns, 150 mA, 5 V, generic array logic
National
Semiconductor
PRELIMINARY
GAL6001® Generic Array Logic
General Description
Using a high performance E2CMOSTM technology, National
Semiconductor has produced a next-generation program-
mable logic device, the GAL6001. Having an FPLA architec-
ture, known for its superior flexibility in state-machine de-
sign, the GAL6001 offers the highest degree of functional
integration, flexibility, and speed currently available in a 24
pin, SOO-mil package.
The GAL6001 has ten programmable Output Logic Macro.
Cells (OLMC) and eight programmable "buried" State Logic
MacroCells (SLMC). In addition, there are ten input Logic
MacroCelIs (ILMC) and ten l/O Logic MacroCells (IOLMC).
Two clock inputs are provided for independent control of
the input and output macrocells.
Advanced features that simplify programming and reduce
test time, coupled with EZCMOS reprogrammable cells, en-
able 100% AC, DC, programmability, and functionality test-
ing of each GAL6001 during manufacture. This allows Na-
tional to guarantee 100% performance to specifications. In
addition, data retention of 20 years and a minimum of 100
erase/write cycles are guaranteed.
Programming is accomplished using standard hardware and
software tools. In addition, an Electronic Signature word is
available for storage of user specified data, and a security
cell ls provided to protect proprietary designs.
Features
a Electrically erasable cell technology
-- Instantly reconfigurable logic
- Instantly reprogrammable cells
- Guaranteed 100% yields
a High performance E2CMOS technology
- Low power: 150 mA maximum
- High speed:
15 ns max. clock to output delay
25 ns max. setup time
30 ns max. propagation delay
I: TTL compatible inputs and outputs
II Unprecedented functional density
- 10 output logic macrocells
- 8 state logic macrocells
- 20 input and VO logic macrocells
n High-level design flexibility
- 78 x 64 x 36 FPLA architecture
- Separate state register and input clock pins
- Functionally supersets existing 24-pin PAL0 and
IFLTM devices
- Asynchronous clocking
n 24-pin, SOO-mil DIP or 28-iead PLCC
a High speed programming algorithm
a 20-year data retention
Block Diagram " GAL6001
NPUTS__ il
2-11 m:
- swc ou'mns
-CI- ”-23
W OUTPUT
TL/L/10561-1
l009'lV9
GAL6001
Absolute Maximum Ratings
Supply Voltage Vcc
Input Voltage Applied
Ott-state Output Voltage Applied
Storage Temperature
-0.5 to + 7V
-0.5 to VCC + 1.0V
- 0.5 to Vcc + 1.0V
- 40'C to + 85''C
Recommended Operating Conditions
SUPPLY VOLTAGE AND TEMPERATURE
Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress only ratings and functional operation of the
device at these or at any other conditions above those indi-
cated in the operational sections of this specification is not
implied (while programming, follow the programming specifi-
cations).
Temperature Range
Symbol Parameter Commercial industrial Units
Mlit Typ Max Min Typ Max
Voc Supply Voltage 4.75 5 5.25 4.5 5 5.5 V
TA Ambient Temperture 0 75 -40 85 'C
Tc Case Temperature tl 75 -40 85 "C
Capacitance (Note 1) (TA = 25'C,t = 1.0 MHz)
Symbol Parameter Test Conditions Maxlmum* Unlts
C. InputCapacitance VCC = 5.0V, V. = 2.0V 8 pF
Co OutputCapacitance Vcc = 5.0V, V0 = 2.0V 10 pF
CB BidirectionalPin Cap Vcc == 5.OV, VB = 2.0V 10 pF
'Guaranteed but not 100% tested.
Switching Test Conditions
Input Pulse Levels GND to 3.0V +sv
Input Rise and Fall Times 5 ns (0.3V to 2.7V)
Input Timing Reference Levels 1.5V From Output (tlx, Fx) R T
Output Timing Reference Levels 1.5V Under Test ttsi Pelnt
Output Load See Figure 600l1 CL .
3-state levels are measured 0.5V from steady-state active
level. =
TL/Lt10561-2
GAL6001 Reset Timing Specifications
'tk. includes jig and probe total capacitance
Symbol Parameter Min Typ Max Unlts
tPR Reset Circuit Power-Up 100 ns
tRESET Register Reset Time trom Valid Vcc 45 Ms
Electrical Characteristics over recommended operating conditions
L009'IVE)
Symbol Parameter Test Conditions J,',',',',',',', Min Max Unlts
IIH, IIL Input Leakage Current GND s VIN s Vcc Max 1 10 pA
IBZH, IBZL Bidirectional Pin Leakage Current GND s VIN 3 Vet: Max i 10 MA
ICC Operating Power Supply Current = 15 MHz COM'L 150 mA
Vcc = Vcc Max IND 180 mA
log Output Short Circuit (Note 1) VCC = 5.0V, VOUT = GND -30 - 130 mA
VOL Output Low Voltage Vcc C. IOL = 16 mA COM/IND 0.5 V
Vcc Min
VOH Output High Voltage Vcc C. loH = --3.2 mA COM/IND 2.4 V
Vcc Min
VIH Input High Voltage 2.0 Vcc + 1 V
" Input Low Vortage 0.8 V
Note 1: One Output at a time for a maximum duration of one second.
Switching Characteristics over recommended operating conditions
Test 6001-30 6001-35
Symbol Parameter Conditions COM COMM Units
R(n) Ct. (pF) Min Max Min Max
tDva Delay from Input or IIO to Output (Note 1) 300 50 30 3540 ns
ttNair Delay from Input or IIO to Outputs Ott (Disable) Infinite 5 25 3035 ns
tDVQv2 Delay from Input or IIO to Outputs On (Enable) Infinite 50 25 3035 ns
tpvm H Input or 1/0 Setup Time to OCLK 300 50 25 30 ns
tm HDX Input or I/O Hold Time after OCLK 300 50 - 5 _ 5 ns
tC1HQv OCLK to Output Valid Delay 300 50 15 17.5 ns
Period 1 OCLK Cycle Time(tovc1H + tc1Hov) 300 50 40 47.5 ns
tDVD1V Input or IIO Setup Time to Sumterm CLK 300 50 7.5 8 ns
tmvpx Input or l/O Hold Time after Sumterm CLK 300 50 12.5 15 ns
tDIvav Sumterm CLK to Output Delay 300 50 35 40 ns
Period 2 STCLK Cycle Time (tDVD1V + tmvov) 300 50 42.5 48.5 ns
tDvch Input or 1/0 Setup Time to ICLK 300 50 2.5 3.5 ns
tchDX Input or IIO Hold Time after ICLK 300 50 5 6 ns
tchQV Delay from ICLK to Asynchronous Output Valid 300 50 35 40 ns
1021101 H Register Setup Time after ICLK 300 50 30 35 ns
tDVCQL Input or I/O Setup Time to Latch 300 50 2.5 3.5 ns
tchDx Input or I/O Hold Time after Latch 300 50 5 6 ns
tRESET Input, l/O or Feedback to Reset 40 45 ns
Note 1:T = Time D = Data a = Output Z = Hi-Z V = Valid H = High L = Low X = Change C1 = OCLK Cl? = ICLK D1 = Sumterm Clock
Differential Product Term (DPT)
Switching Characteristics
The number of DPT that may switch in the same direction at the same time is limited to a maximum of 15.
The number of DPT for a given design is calculated by subtracting the total number of Product-Terms that are switching from a
Logical HI to a Logical LO from those switching from a Logical LO to a Logical HI within a 5 ns period.
DPT = (P-Terms)LH-(P-Terms)HL
GAL6001
28-Lead PLCC Connection Diagram
" CLK/IO VCC
24-PIN
ts!.,,-,!',,'.;).-.)', El El " I E] il
NUMBERS
28-LEAD PLCC
(TOP VIEW)
GAL6001 Block Diagram-DIP Connections
CLK/IO [2] l: V ca 1281
n [s] E El i271
I2 [41 a Eil 1261
l3 [51 E 211 [251
I4 Itil E El WI
Is m LE El [231
l6 191 Ct GAL 6001 E ml
I7 [10] CE El i20l
Is " l 1 CE E " 9]
i9 U21 IE El I18]
no [13] it, E4] 117l
GND [14] [E Coil 1161
[PLcc Pin Numbers]
TL/L/1056t.-3
TL/L/10561 -4
Input Logic MacroCell (ILMC) and
I/O Logic MacroCell (IOLMC)
The GAL6001 features two configurable input sections. The
ILMC section corresponds to the dedicated input pins (2-
11) and the IOLMC to the I/O pins (14-23). Each input
section is configurable as a block for asynchronous,
latched, or registered inputs. Pin 1 (iCLK) is used as an
enable input for latched macroceils (transparent when high)
and as a clock for registered macroceils (positive edge trig-
gered).
Configurable input blocks can be used to advantage by sys-
tem designers. Registered inputs are popular for synchroni-
zation and data merging. Transparent latches are useful
when the input data is invalid outside a known time window.
Direct inputs are used in systems where the input data is
well ordered in time. With the GAL6001, external registers
and latches are not necessary.
The various configurations ot the input and IIO macroceils
are controlled by programming tour architecture control bits
(iNLATCH, INSYN, IOLATCH, and IOSYN) within the 68-bit
architecture control word. The SYN bits determine whether
the macroceils will have register/Iatch capability or will be
strictly asynchronous. The LATCH bits select between
latched and registered inputs.
The three valid macroceil configurations are shown in the
macroceil equivalent diagrams on the following pages The
truth table associated with each diagram shows the values
of the LATCH and SYN bits required to set the macroceil to
the configuration shown.
Output Logic MacroCell (OLMC)
and State Logic MacroCell (SLMC)
The outputs of the OR array feed two groups of macroceils.
One group of eight macroceils is buried; its outputs teed
back directly into the AND array rather than to device pins.
These cells are called the State Logic MacroCeIls (SLMC),
as they are useful for building state machines. The second
group of macroceils consists of 10 cells whose outputs, in
addition to feeding back into the AND array, are available at
the device pins. Cells in this group are known as Output
Logic MacroCeIls (OLMC).
Like the ILMC and iOLMC discussed above, output and
state logic macroceils are configured by programming spe-
cific bits in the architecture control word (CKS(i), OUT-
SYN(i), XORDU), XORE(i)), but unlike the input macroceils
which must be configured in blocks, these macroceils are
configurable on a matxocall-by-macrocell basis. Throughout
this datasheet, i = [14 . . . 23] for OLMCs and i = [0 . . . 7]
for SLMCs.
State and Output Logic MacroCeIls may be set to one of
three valid configurations: combinational. D-type registered
with sum term (asynchronous) clock, or D/E-type regis-
tered. Output macroceils always have l/O capability, with
directional control provided by the 10 output enable (OE)
product terms. Additionally, the polarity of each OLMC out-
put is selectable through the XORD(i) architecture bits. Po-
larity selection is not necessary for SLMCs, since both the
true and complemented forms of their outputs are available
in the AND array. Polarity of all "E" sum terms is selectable
through the XORE(i) architecture control bits.
When CKS(i) = 1 and OUTSYN(i) = 0, macroceil "i'' is set
as "D/E-typa registered". In this configuration, the register
is clocked from the common OCLK and the register clock
enable input is controlled by the associated "E" sum term.
This configuration is useful for building counters and state-
machines with state hold functions.
When CKS(i) = 0 and OUTSYN(i) = 0, macroceil "i" is set
as "D-type registered with sum term clock". in this configu-
ration, the register is enabled and its "E" sum term is routed
directly to the clock input. This allows for the popular "asyn-
chronous programmable clock" feature, selectable on a
register-by-register basis.
When CKS(i) = 0 and OUTSYN(i) = 1, macroceil "i" is set
as "combinatorial". Configuring a SLMC in this manner
turns it into a complement array. Complement arrays are
used to construct multi-Ievei logic.
Registers in both the Output and State Logic MacroCeIls
feature a RESET input. This active high input allows the
registers to be simultaneously and asynchronously reset
from a common signal. The source of this signal is the HE-
SET product term. Registers reset to a logic zero, but since
the output buffers invert, a logic one will be present at the
device pins.
There are two possible feedback paths from each OLMC:
one from before the output buffer (this is the normal path)
and one from after the output buffer, through the IOLMCs.
The second path is usable as a feedback only when the
associated bi-directional pin is being used as an output; dur-
ing input operations it becomes the input data path, turning
the associated OLMC into an additional buried state macro-
The DIE registers used in this device offer the designer the
ultimate in flexibility and utility. The D/ E register construct
can emulate RS-, JK-, and T-type registers with the same
efficiency as a dedicated RS-, JK- or T-register.
The three valid macroceil configurations are shown in the
macroceil equivalent diagrams on the following pages. The
truth table associated with each diagram shows the bit val-
ue of CKS(i) and OUTSYN(i) required to set the macroceil to
the configuration shown.
l-OOQ'IVE)
GAL6001
ILMCIIOLMC Configurations
ILMCIIOLMC Generic Block Dlagram
TL/Lf1056t-5
,--- ---------------
I UEtuL-- 01
Imn ms 2-11 I y m
on o to to
I/o ms 14-23 I 10 n
k---------)-
Registered Input
--- ---------------,
Imn PINS 2-"
l/O ms 14-23 10
--—--J
p---------—--‘
INPUT PINS 2-11
I/O PINS 14-13
INPUT PINS 2-11
I/O PINS “-25
Asynchronous Input
---l-----------,
'---—----—--ooq
, ' Do:
.-------_._..r.ii.t_.t---.----
TL/l./1056t-8
LATCH SYN
TL/L/10561-11
OUTSYNU)
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l---------------------
GAL6001
OLMC/SLMC Configurations (Continued)
Combinatorial
tO AND
f OE l
RESU I n (I) I0uic i
[T-i/ii-V- ............... I. .......... -F- --.' E
I t XORDO) OLMC I " t I '
, l 0qu I I ' I
D I ',, D i ' I . W ,
Faun I K ---------- J % - j-o-e-e'-''
on ' I
ARRAY i I CKS0) OUTSYN(l)
: -r- nu I
I t tl 1
Array Description
The GAL6001 E2 reprogrammable array is subdivided into
three smaller arrays: AND, OR and Architecture. These ar-
rays are described in detail below.
AND ARRAY
The AND array is organized as 78 input terms by 75 product
term outputs. The 20 input and I/O logic macrocells, 8
SLMC feedbacks, 10 OLMC feedbacks, and ICLK comprise
a total of 39 inputs to this array (each available in true and
complemented forms). Product terms 0-63 serve as inputs
to the OR array. Product term 64 is the RESET PT; it gener-
ates the RESET signal described in the earlier discussion of
output and state logic macrocells. Product terms 65-74 are
the output enable product terms; they control the output
buffers, thus enabling device pins 14-23 to be bi-direction
or TRI-STATE)
OR ARRAY
The OR array is organized as 64 inputs by 36 sum term
outputs. Product terms 0-63 of the AND array serve as the
inputs to this array. Of the 36 sum term outputs, 18 are data
CD") terms and 18 are enable/clock CE") terms. These
terms feed into the 10 OLMCs and 8 SLMCs, one "D" term
and one "E'' term to each.
ARCHITECTURE ARRAY
The various configurations of the GAL6001 are enabled by
programming cells within the architecture control word. This
68-bit word contains all of the chip configuration data. This
data includes: XORDU), XORE(i), CKS(i), OUTSYN(i),
INLATCH, INSYN, lOLATCH, and lOSYN. The function of
each of these bits has been previously explained.
Electronic Signature Word
Every GAL6001 device contains an electronic signature
word. The Electronic Signature word is a 72-bit user defin-
able storage area, which can be used to store inventory
control data, pattern revision numbers, manufacture date,
etc. Signature data is always available to the user, regard-
less of the state of the security cell.
Security Cell
A security cell is provided with every GAL6001 device as a
deterrent to unauthorized copying of the array patterns.
TL/t.f1056t-18
Once programmed, this cell prevents further read access to
the AND, OR and architecture arrays. This cell can be
erased only during a bulk erase cycle, so the original config-
uration can never be examined once this cell is pro-
grammed. Electronic Signature data is always available to
the user, regardless of the state of this control cell.
Bulk Erase
Before writing a new pattern into a previously programmed
part, the old pattern must first be erased. This erasure is
done automatically by the programming hardware as part of
the programming cycle and takes only 50 ms.
Register Preload
When testing state machine designs, all possible states and
state transitions must be verified, not just those required
during normal machine operations. This is because in sys-
tem operation, certain events may occur that cause the log-
ic to assume an illegal state: power-up, brown out, tine volt-
age glitches, etc. To test a design for proper treatment of
these conditions, a method must be provided to break the
feedback paths and force any desired state (i.e., illegal) into
the registers. Then the machine can be sequenced and the
outputs tested for correct next state generation.
All of the registers in the GAL6001 can be preloaded, in-
cluding the input, I/O, and state registers. In addition, the
contents of the state and output registers can be examined
in a special diagnostics mode. Programming hardware takes
care of all preload timing and voltage requirements.
Input Buffers
GAL devices are designed with TTL level compatible input
buffers. These buffers, with their characteristically high im-
pedance, load driving logic much less than "traditional bipo-
lar devices". This allows for a greater fan out from the driv-
ing logic.
GAL devices do not possess active pull-ups within their in-
put structures. As a result, National recommends that all
unused inputs and TRI-STATE l/O pins be connected to
another active input, Vcc, or GND. Doing this will tend to
improve noise immunity and reduce ICC for the device.
Power-Up Reset
Circuitry within the GAL6001 provides a reset signal to all
registers during power-up. All internal registers will have
their Q outputs set low after a specified time (tn ESET). As a
result, the state on the registered output pins (if they are
enabled) will always be high on power-up. regardless of the
programmed polarity of the output pins. This feature can
greatly simplify state machine design by providing a known
state on power-up.
The timing diagram for power-up is shown above Because
of the asynchronous nature of system power-up, the follow-
ing conditions must be met to guarantee a valid power-up
reset of the GAL6001. First, the V00 rise must be monoton-
kt. Second, the clock inputs must become a proper ITL
level within the specified time (tPR). The registers will reset
within a maximum of tRESET time. As in normal system
operation, avoid clocking the device until all input and feed-
back path setup times have been met.
Voc 90X
av -2%
Icu< hr; '00000l
ocu< vlL AAAAAA
-ttstt
VALID CLOCK SIGNAL
ttrss,
INTERNAL REGISTER
Jl'si'lh J2g222222222222222g2trCa'iliCr
FEEDBACK/EXTERNAL v
Ti'liifl (XI
Ordering Information
2K1222g2222222j227
EXTERNAL REGISTER
OUTPUT = LOGIC 1
TLfLt1056t-13
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
Device Number
GAL 6001 -30 L N C
Generic Array Logic Family
-30 = 30 nst
-35 = 35 nsth
L = HalfPower
(150 mA for GAL6001)
Package Type:
N = 24-Pin Plastic DIP
J = 24-Pin Ceramic DIP
V = 28-Lead Plastic Chip Carrier (PLCC)
Temperature Range:
C = Commercial (0°C to +75')
l = Industrial (-40°C to +85°C)
L009'IV9
GAL6001
GAL6001 Logic Diagram
TL/L/10561-15
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
GAL6001-30LJl - product/gal6001-30lji?HQS=T|-nuIl-nu|I-dscatalog-df-pf-nulI-wwe
GAL6001-30LNC - productlgal6001-30|nc?HQS=T|-nulI-null-dscataIog-df-pf-null-wwe
GAL6001-30LNl - product/gal6001-30lni?HQS=T|-nu|I-nulI-dscatalog-df-pf-nulI-wwe
GAL6001-30LVC - product/gal6001-30Ivc?HQS=T|-nu|I-nuII-dscatalog-df—pf-null-wwe
GAL6001-30LVl - product/gal6001-30|vi?HQS=TI-nu|I-nulI-dscatalog-df-pf-null-wwe
GAL6001-35LJC - productlgal6001-35|jc?HQS=T|—nu||-nu|I-dscatalog-df-pf-null-wwe
GAL6001-35LJI - product/gal6001-35lji?HQS=T|—nuIl—nu|I-dscatalog-df-pf-nulI-wwe
GAL6001-35LNC - product/gal6001-35|nc?HQS=T|—null-nu|I—dscataIog-df—pf-null-wwe
GAL6001-35LNI - product/gal6001-35lni?HQS=T|-nu|I-null-dscatalog-df-pf—nuII-wwe
GAL6001-35LVC - product/gal6001-35|vc?HQS=T|-nulI-nuII-dscatalog-df—pf—null-wwe
GAL6001-35LVI - product/gal6001-35|vi?HQS=T|-nu|I-nulI-dscatalog-df-pf-nulI-wwe
GAL6001-30LJC - product/gal6001-30|jc?HQS=T|-nu|I-null-dscatalog-df-pf-null-wwe
