FSTUD32450GX ,Configurable 4-Bit to 40-Bit Bus Switch with -2V Undershoot Protection and Selectable Level ShiftingFeaturesThe Fairchild Universal Bus Switch FSTUD32450 provides Undershoot protected to −2V (A and ..
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FSTUD32450GX
Configurable 4-Bit to 40-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting
FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with −2V Undershoot Protection and Selectable Level Shifting August 2001 Revised July 2002 FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with −2V Undershoot Protection and Selectable Level Shifting General Description Features The Fairchild Universal Bus Switch FSTUD32450 provides � Undershoot protected to −2V (A and B Ports) 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed � Voltage level shifting CMOS TTL-compatible bus switching. The low On Resis- � 4Ω switch connection between two ports tance of the switch allows inputs to be connected to out- � Minimal propagation delay through the switch puts without adding propagation delay or generating � Low l additional ground bounce noise. CC The FSTUD32450 is designed to allow “customer” configu- � Zero bounce in flow-through mode ration control of the enable connections. The device can be � Control inputs compatible with TTL level organized as either a ten 4-bit, eight 5-bit, four 10-bit, two � See Applications Notes AN-5008 and AN-5021 for UHC 20-bit or one 40-bit enabled bus switch. Also achievable details are 8-bit and 16-bit enabled configurations (see Functional � Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Description). The device's bit configuration is controlled through select pin logic. (see Truth Table). When OE is x Applications Note LOW, Port A is connected to Port B . When OE is HIGH, x x x the switch is OPEN. Select pins S , S , S , S , S and S are intended to be 0 1 2 3 4 5 The A and B Ports are protected against undershoot to used as static user configurable control pins. The AC per- support an extended range to 2.0V below ground. formance of these pins has not been characterized or Fairchild's integrated Undershoot Hardened Circuit tested. Switching of these select pins during system opera- (UHC) senses undershoot at the I/O, and responds by tion may temporarily disrupt output logic states and/or preventing voltage differentials from developing and turn- enable pin controls. ing the switch on. 40-bit configuration can be achieved by connecting the Another innovative device feature is the addition of a level OE and the OE pins to together. 1 6 shifting select pin, “S and S ”. When S and S are LOW, 2 5 2 5 the device behaves as a standard N-MOS switch. When S 2 and S are HIGH, a diode to V is integrated into the cir- 5 CC cuit allowing for level shifting between 5V inputs and 3.3V outputs. Ordering Code: Order Number Package Number Package Description FSTUD32450G BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. UHC is a trademark of . © 2002 DS500447
