FSTUD16450MTDX ,Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level ShiftingFeaturesThe Fairchild Universal Bus Switch FSTUD16450 provides
FSTUD16450MTDX
Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting
FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting January 2001 Revised August 2001 FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting General Description Features The Fairchild Universal Bus Switch FSTUD16450 providesUndershoot hardened to −2V (A and B Ports) 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOSVoltage level shifting TTL-compatible bus switching. The low On Resistance of 4Ω switch connection between two ports the switch allows inputs to be connected to outputs without Minimal propagation delay through the switch adding propagation delay or generating additional ground Low l bounce noise. CC The FSTUD16450 is designed to allow “customer” configu-Zero bounce in flow-through mode ration control of the enable connections. The device is Control inputs compatible with TTL level organized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch. See Applications Note AN-5008 for details 8-bit and 16-bit configurations are also achievable (see Also packaged in plastic Fine-Pitch Ball Grid Array Functional Description). The device's bit configuration is (FBGA) (Preliminary) chosen through select pin logic. (see Truth Table). When OE is LOW, Port A is connected to Port B . When OE is x x x x Applications Note HIGH, the switch is OPEN. The A and B Ports are “undershoot hardened” with UHC Select pins S , S , S are intended to be used as static 0 1 2 protection to support an extended range to 2.0V below user configurable control pins. The AC performance of ground. Fairchild's integrated “Undershoot Hardened these pins has not been characterized or tested. Switching Circuit” (UHC) senses undershoot at the I/O's, and of these select pins during system operation may tempo- responds by preventing voltage differentials from develop- rarily disrupt output logic states and/or enable pin controls. ing and turning on the switch. Another key device feature is the addition of a level shifting select pin, “S ”. When S is LOW, the device behaves as a 2 2 standard N-MOS switch. When S is HIGH, a diode to V 2 CC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs. Ordering Code: Order Number Package Number Package Description FSTUD16450GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1) (Preliminary) [Tape and Reel] FSTUD16450MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1: BGA package available in Tape and Reel only. UHC is a trademark of . © 2001 DS500391
