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FQD4P25FAIRCHILN/a25200avai250V P-Channel MOSFET


FQD4P25 ,250V P-Channel MOSFETFQD4P25 / FQU4P25December 2000TMQFET QFET QFET QFETFQD4P25 / FQU4P25250V P-Channel MOSFET
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FQD4P25
250V P-Channel MOSFET
FQD4P25 / FQU4P25 December 2000 TM QFET QFET QFET QFET FQD4P25 / FQU4P25 250V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect  -3.1A, -250V, R = 2.1Ω @V = -10 V DS(on) GS transistors are produced using Fairchild’s proprietary,  Low gate charge ( typical 10 nC) planar stripe, DMOS technology.  Low Crss ( typical 10.3 pF) This advanced technology is especially tailored to minimize  Fast switching on-state resistance, provide superior switching  100% avalanche tested performance, and withstand a high energy pulse in the  Improved dv/dt capability avalanche and commutation modes. These devices are well suited for high efficiency switching DC/DC converters. S !!!!!!!! D ●●●●●●●● ●●●● G!!!!!!!! ●●●● ▶▶▶▶▶▶▶▶ ▲▲▲▲▲▲▲▲ ●●●●●●●● D-PAK I-PAK G S FQD Series G FQU Series D S !!!! !!!! D Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQD4P25 / FQU4P25 Units V Drain-Source Voltage -250 V DSS I - Continuous (T = 25°C) Drain Current -3.1 A D C - Continuous (T = 100°C) -1.96 A C I (Note 1) Drain Current - Pulsed -12.4 A DM V Gate-Source Voltage ± 30 V GSS E (Note 2) Single Pulsed Avalanche Energy 280 mJ AS I Avalanche Current (Note 1) -3.1 A AR E (Note 1) Repetitive Avalanche Energy 4.5 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) -5.5 V/ns Power Dissipation (T = 25°C) * 2.5 W P A D Power Dissipation (T = 25°C) 45 W C - Derate above 25°C 0.36 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8” from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 2.78 °C/W θJC R Thermal Resistance, Junction-to-Ambient * -- 50 °C/W θJA R Thermal Resistance, Junction-to-Ambient -- 110 °C/W θJA * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A2, December 2000
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