FQD2P40 ,400V P-Channel MOSFETFQD2P40 / FQU2P40December 2000TMQFET QFET QFET QFETFQD2P40 / FQU2P40400V P-Channel MOSFET
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FQD2P40
400V P-Channel MOSFET
FQD2P40 / FQU2P40 December 2000 TM QFET QFET QFET QFET FQD2P40 / FQU2P40 400V P-Channel MOSFET General Description Features These P-Channel enhancement mode power field effect -1.56A, -400V, R = 6.5Ω @V = -10 V DS(on) GS transistors are produced using Fairchild’s proprietary, Low gate charge ( typical 10 nC) planar stripe, DMOS technology. Low Crss ( typical 6.5 pF) This advanced technology is especially tailored to minimize Fast switching on-state resistance, provide superior switching 100% avalanche tested performance, and withstand a high energy pulse in the Improved dv/dt capability avalanche and commutation modes. These devices are well suited for electronic lamp ballasts based on the complementary half bridge topology. S !!!!!!!! D ●●●●●●●● ●●●● G!!!!!!!! ●●●● ▶▶▶▶▶▶▶▶ ▲▲▲▲▲▲▲▲ ●●●●●●●● D-PAK I-PAK G S FQD Series G FQU Series D S !!!! !!!! D Absolute Maximum Ratings T = 25°C unless otherwise noted C Symbol Parameter FQD2P40 / FQU2P40 Units V Drain-Source Voltage -400 V DSS I - Continuous (T = 25°C) Drain Current -1.56 A D C - Continuous (T = 100°C) -0.98 A C I (Note 1) Drain Current - Pulsed -6.24 A DM V Gate-Source Voltage ± 30 V GSS E (Note 2) Single Pulsed Avalanche Energy 120 mJ AS I Avalanche Current (Note 1) -1.56 A AR E (Note 1) Repetitive Avalanche Energy 3.8 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) -4.5 V/ns Power Dissipation (T = 25°C) * 2.5 W P A D Power Dissipation (T = 25°C) 38 W C - Derate above 25°C 0.3 W/°C T , T Operating and Storage Temperature Range -55 to +150 °C J STG Maximum lead temperature for soldering purposes, T 300 °C L 1/8” from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 3.29 °C/W θJC R Thermal Resistance, Junction-to-Ambient * -- 50 °C/W θJA R Thermal Resistance, Junction-to-Ambient -- 110 °C/W θJA * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A2, December 2000
