FOA3251B1 Fast Delivery |IC PHOENIX CO.,LIMITED

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FOA3251B1
High Speed Clock and Data Recovery for Fiber Optic Applications

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FOA3251B1
S1028C1
Revision History:1999-08V1.0
Previous Version:
Preface
The transceiver IC FOA3251 is designed for fibre optic application in the data bit range
of 2.5GBit. The FOA3251 fulfills the jitter requirements specified in ITUG958 and
Bellcore GR253.
Organization of this Document
This Data Sheet is divided into 8 chapters. It is organized as follows:Chapter1, Overview
Gives a general description of the product , lists the key features, and presents some
typical applications.Chapter2, Functional Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
Blockdiagram and block description.Chapter3, Operational DescriptionChapter4, Electrical Characteristics
DC and AC Characteristics, Power consumption, interface specification.Chapter5, External Components
Application notes and recommended suppliersChapter6, Measurement ResultsChapter7, Package Outlines
Table of ContentsPageOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1Operating States of Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
High Speed Clock and Data Recovery for
Fiber Optic Applications
FOA3251B1
S1028C1
BIPOLAROverview
The transceiver IC FOA3251 is designed for fibre optic
application in the data bit range of 2.5GBit. The
FOA3251 fulfills the jitter requirements specified in
ITUG958 and Bellcore GR253.
1.1FeaturesData rate up to 2.633 Gb/sAll jitter data meet ITU-TG958 and GR-253-Core
requirementsSupply range from +3.0 V to 5.0 VSupply current < 210 mAInput sensitivity < 5 mVpp differential (BER = 10-12)Loss of signal (LOS) detectionProgrammable delay element to adjust clock- to data outputLock indication
1.2ApplicationsFibre optic communication systemsSDH / SONET / ATM applications
Functional DescriptionThe FOA3251 consists of a clock and data recovery block (CDR), a clock multiplier unit
(CMU) and a programmable delay line.
2.1Pin Configuration (top view)
Figure1Pin Configuration
2.2Pin Definition and Function
Table 1Pin Definition and Function
Table 1Pin Definition and Function (cont’d)
2.3Functional Block Diagram
Figure2Block Diagram
2.4Functional Block Description
The clock and data recovery block (CDR) consists of a bang-bang phase detector (PD),
a frequency window detector (FWD) and a VCO. The PD also provides a kind of
statistical BER signal that is used to generate a loss of signal (LOS) signal. The FWD
moves the VCO in the right frequency range. The frequency window is about 10000 ppm
of the center frequency. When the frequency is out of range a los of lock signal (LOL) is
generated. The center frequency is given by a reference clock signal which is (signal
frequency)/128. The VCO is a 3 stage ring oscillator type.
The clock multiplier unit (CMU) consist of a phase frequency detector (PFD), a VCO and
a retiming Flip-Flop. The PFD is type 4 phase and frequency detector. The low pass
filtered PFD signal as a function of the phase error is shown in Figure3.
Figure3PFD Characteristic
The VCO is a LC type with a center frequency of 2.5GHz. The measured tuning range
is shown in Figure4.
Figure4Tuning Range LC VCO
The delay line is programmable in 8 steps of about 50 ps. The clock signal is adjustable
Operational Description3.1Operating States of Delay Line
For clock to data output adjustment a adjustable delay line is available. The clock output
signal is adjustable by the signals DELAY0..2.
Table 2Truth Table Delay Line
Electrical Characteristics4.1Absolute Maximum Ratings
The RF Pin 40, 42 are not ESD protected. The high frequency performance prohibits the
use of a adequate protective structure. Pin 33 is only protected to VEE.
4.2Operating Range
Table 3Absolute Maximum Ratings
Table 4Operating Range
4.3DC Characteristics
4.4AC Characteristics
Table 5DC Characteristics
Table 6Electrical Characteristics

Partno	Mfg	Dc	Qty	Available	Descript
FOA3251B1	INFINEON	N/a	438	avai	High Speed Clock and Data Recovery for Fiber Optic Applications