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FM25L04B-GTR from RAMTRON, 5000pcs , SOP8 , Alternate PN:FM25L04BGTR,4-Kbit (512 ?8) Serial (SPI) F-RAM
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FM25L04B-GTR RAMTRON N/a 5000

Characteristics ... 13SPI Modes ....5 Power Cycle Timing . 15Power Up to First Access ........6 Ordering Information 16Command Structure .......6 Ordering Code Definitions ..... 16WREN - Set Write Enable Latch ......6 Package Diagrams.... 17WRDI - Reset Write Enable Latch ....6 Acronyms 19Status Register and Write Protection .. 6 Document Conventions .... 19RDSR - Read Status Register .7 Units of Measure . 19WRSR - Write Status Register 7 Document History Page.... 20Memory Operation...... 8 Sales, Solutions, and Legal Information .... 21Write Operation .....8 Worldwide Sales and Design Support ..... 21Read Operation .....8 Products .....21HOLD Pin Operation ......9 PSoCĀ® Solutions 21Endurance ..10 Cypress Developer Community ...... 21Maximum Ratings..... 11 Technical Support ........ 21Operating Range....... 11Document Number: 001-86146 Rev. *D Page 2 of 21FM25L04BPinoutsFigure 1. 8-pin SOIC pinout 8VCS 1DDSO 72 Top View HOLDnot to scale 63SCKWP 5V 4SISSFigure 2. 8-pin TDFN pinoutOVCS 1 8DDSO 2 7HOLDEXPOSEDPADWP 3 6 SCKV SI45SSTop Viewnot to scalePin DefinitionsPin Name I/O Type DescriptionCS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-powerstandby mode, ignores other inputs, and tristates the output. When LOW, the device internallyactivates the SCK signal. A falling edge on CS must occur before every opcode. SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edgeand outputs occur on the falling edge. Because the device is synchronous, the clock frequency maybe any value between 0 and 20 MHz and may be interrupted at any time. [1]SI Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCKand is ignored at other times. It should always be driven to a valid logic level to meet I specifications.DD[1]SO Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all othertimes including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock. WP Input Write Protect. This active LOW pin prevents all write operation, including Status Register. If HIGH,write access is determined by the other write protection
FM25L04-GTR

FM25L04B-GTR ,4-Kbit (512 ?8) Serial (SPI) F-RAMCharacteristics ... 13SPI Modes ....5 Power Cycle Timing . 15Power Up to First Access ........6 Ord ..
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