FIN1028 ,3.3V LVDS 2-Bit High Speed Differential ReceiverFeaturesThis dual receiver is designed for high speed interconnects
FIN1028
3.3V LVDS 2-Bit High Speed Differential Receiver
FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver March 2001 Revised September 2001 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver General Description Features This dual receiver is designed for high speed interconnectsGreater than 400Mbs data rate utilizing Low Voltage Differential Signaling (LVDS) technol-3.3V power supply operation ogy. The receiver translates LVDS levels, with a typical dif- 0.4ns maximum differential pulse skew ferential input threshold of 100 mV, to LVTTL signal levels. 2.5ns maximum propagation delay LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speedLow power dissipation transfer of clock and data.Power-Off protection The FIN1028 can be paired with its companion driver, theFail safe protection for open-circuit, shorted and FIN1027, or any other LVDS driver. terminated conditions Meets or exceeds the TIA/EIA-644 LVDS standard Flow-through pinout simplifies PCB layout 8-Lead SOIC package saves space Ordering Code: Order Number Package Number Package Description FIN1028M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Name Description R , R LVTTL Data Outputs OUT1 OUT2 R , R Non-inverting LVDS Inputs IN1+ IN2+ R , R Inverting LVDS Inputs IN1− IN2− V Power Supply CC GND Ground Function Table Input Outputs R R R IN+ IN+ OUT LH L HL H Fail Safe Condition H TOP VIEW H = HIGH Logic Level L = LOW Logic Level Fail Safe = Open, Shorted, Terminated © 2001 DS500503
