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ESDA6V1W5
QUAL TRANSIL ARRAY FOR ESD PROTECTION
ESDA6V1W5September 1999 - Ed: 1A
QUAL TRANSIL ARRAY
FOR ESD PROTECTION
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
Computers
Printers
Communication systems
GSM handsets and accessories
Other telephone sets
Set top boxes
MAIN APPLICATIONSApplication Specific Discretes
A.S.D.
FUNCTIONAL DIAGRAM4 unidirectional TRANSIL functions.
Breakdown voltage : VBR = 6.1 V min.
Low leakage current : < 1μA.
Very low PCB space consuming : 4.2 mm2 typically.
FEATURES
DESCRIPTIONThe ESDA6V1W5 is a 4-bit wide monolithic
suppressor which is designed to protect component
connected to data and transmission lines against
ESD.
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
BENEFITSHigh ESD protection level : up to 25 kV.
High integration.
Suitable for high density boards.
IEC 1000-4-2 level 4
MIL STD 883C-Method 3015-6 : class 3.
(human body model)
COMPLIES WITH THE FOLLOWING STANDARDS :
ESD RESPONSE TO IEC1000-4-2
(air discharge 16 kV, positive surge)1/7
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)
note 1 : Square pulse Ipp = 15A, tp=2.5μs.
note 2 : Δ VBR = αT* (Tamb -25°C) * VBR (25°C)
ESDA6V1W52/7
The ESDA family has been designed to clamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage VCL.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20μs and 10/1000μs surges.
2.5μs duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20μs, the
2.5μs rectangular surge is well adapted. In addition
both rise and fall times are optimized to avoid any
parasitic phenomenon during the measurement of
Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
ESDA6V1W53/7
50 75 100 125 1501
IR[Tj] / IR[Tj=25°C]
Fig. 5 : Relative variation of leakage currentversus junction temperature (typical values).
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.41E-3
1E-2
1E-1
1E+0
IFM(A)
Fig. 6 : Peak forward voltage drop versus peakforward current (typical values). 5 10 15 20 25 300.1
Ipp(A)
Fig. 3 : Clamping voltage versus peak pulse
current (Tj initial = 25 °C).
Rectangular waveform tp = 2.5 μs.
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.010
C(pF)
Fig. 4 : Capacitance versus reverse appliedvoltage (typical values). 25 50 75 100 125 150 1750.0
Ppp[Tj initial]/Ppp[Tj initial=25°C]
Fig. 1 : Peak power dissipation versus initial
junction temperature 10 10010
Ppp(W)
Fig. 2 : Peak pulse power versus exponential
pulse duration (Tj initial = 25 °C)
ESDA6V1W54/7
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.
Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in
suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such
that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the
transient current to ground.
1. ESD protection by the ESDA6V1W5Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
The ESDA6V1W5 should be placed as near as possible to the input terminals or connectors.
Minimise the path length between the ESD suppressor and the protected device
Minimise all conductive loops, including power and ground loops
The ESD transient return path to ground should be kept as short as possible.
Use ground planes whenever possible.
2. Circuit Board LayoutThe ESDA6V1W5 array is the ideal product for use as board level protection of ESD sensitive
semiconductor components.
The tiny SOT323-5L package makes the ESDA6V1W5 device some of the smallest ESD protection
devices available. It also allows design flexibility in the design of "crowded" boards where the space saving
is at a premium. This enables to shorten the routing and can contribute to improved ESD performance.
ESDA6V1W55/7
PACKAGE MECHANICAL DATASOT323-5L
FOOT PRINT (in millimeters)
ORDER CODE
ESDA6V1W56/7
