ESDA6V1U1RL ,TRANSIL ARRAY FOR ESD PROTECTIONFEATURESn 6 UNIDIRECTIONAL TRANSIL FUNCTIONSFUNCTIONAL DIAGRAMn LOW LEAKAGE CURRENT: I max. < 2 μAR ..
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ESDA6V1U1RL
TRANSIL ARRAY FOR ESD PROTECTION
1/6
ESDA6V1U1August 2002 - Ed:3A
FUNCTIONAL DIAGRAMTRANSIL ARRAY
FOR ESD PROTECTION
Application Specific Discretes
A.S.D.
BENEFITSHigh ESD protection level:upto25kV
High integration
Suitablefor high density boards
IEC61000-4-2: level4
MIL STD 883C-Method 3015-6: class3
(human body model)
COMPLIES WITHTHE FOLLOWINGSTANDARDS:Where transient overvoltage protectionin ESD
sensitive equipmentis required, suchas: COMPUTERS PRINTERS COMMUNICATION SYSTEMS GSM HANDSETS AND ACCESSORIES CAR RADIOis particulary recommended for parallel port
protection where the line interface withstands onlykV ESD surge.
APPLICATIONS6 UNIDIRECTIONAL TRANSIL FUNCTIONS LOW LEAKAGE CURRENT:IR max.<2 μA 200W PEAK PULSE POWER (8/20 μs)
FEATURES
DESCRITIONThe ESDA6V1U1 is a monolithic voltage
suppressor designedto protect components which
are connectedto data and transmission lines
against ESD. clamps the voltage just above the logic level
supplyfor positive transients, andtoa diode drop
below groundfor negative transients.
ESDA6V1U1
ELECTRICAL CHARACTERISTICS (Tamb =25°C)
ABSOLUTE MAXIMUM RATINGS (Tamb= 25°C)
note1: Square pulse, Ipp= 25A, tp=2.5μs.
note2: ΔVBR= αT*(Tamb -25°C) *VBR (25°C)
ESDA6V1U1The ESDA family has been designedto clamp fast
spikes like ESD. Generally the PCB designers
needto calculate easily the clamping voltage VCL.
Thisis why we give the dynamic resistancein
additionto the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL =VBR +Rd IPP
WhereIpp isthe peak current through the ESDA cell.
DYNAMIC RESISTANCE MEASUREMENTThe short durationof the ESD has ledusto prefer more adapted test wave,as below defined,to the
classical 8/20μs and 10/1000μs surges.
2.5μs duration measurement wave. the valueof the dynamic resistance remains
stable fora surge duration lower than 20μs, the
2.5μs rectangular surge is well adapted. In
addition both rise and fall times are optimizedto
avoid any parasitic phenomenon during the
measurementof Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
ESDA6V1U1
Fig.1: Peak power dissipation versus initial
junction temperature.
Fig.3: Clamping voltage versus peak pulse
current(Tj initial=25 °C).
Rectangular waveformtp= 2.5 μs.
Fig.2: Peak pulse power versus exponential
pulse duration(Tj initial=25 °C).
Fig.5: Relative variationof leakage current
versus junction temperature (typical values).
Fig. 6 : Peak forward voltage drop versus peak
forward current (typical values).
Fig.4: Capacitance versus reverse applied
voltage (typical values).
ESDA6V1U1
APPLICATION EXAMPLE: Protectionof logic-level signals.
APPLICATION EXAMPLE: Protectionof symmetrical signals.
Note: Capacitance value between any I/O pin and Groundis dividedby2.
ESDA6V1U1
PACKAGE MECHANICAL DATASO-8 Plastic
Packaging: Preferred packagingis tape and reel.
Weight: 0.08g.
Information furnishedis believedtobe accurateandreliable. However, STMicroelectronicsassumesno responsibilityforthe consequencesof
useof suchinformation norfor anyinfringementof patents orother rights ofthird parties whichmay result fromitsuse.Nolicenseisgrantedby
implicationor otherwise underany patentor patent rightsof STMicroelectronics. Specifications mentionedinthis publicationare subjectto
change without notice. This publication supersedesand replacesall information previously supplied.
STMicroelectronics productsarenot authorizedforuseas critical componentsinlife support devicesor systems without express writtenap-
provalof STMicroelectronics.
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