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ESDA6V1P6STMN/a10000avaiQUAD TRANSIL ARRAY FOR ESD PROTECTION


ESDA6V1P6 ,QUAD TRANSIL ARRAY FOR ESD PROTECTIONFEATURESn 4 UNIDIRECTIONAL TRANSIL™ FUNCTIONS.n BREAKDOWN VOLTAGE V = 6.1V MINBRn LOW LEAKAGE CURRE ..
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ESDA6V1P6
QUAD TRANSIL ARRAY FOR ESD PROTECTION
ESDA6V1P6
QUAD TRANSIL™ ARRAY
FOR ESD PROTECTION
Where transient overvoltage protectionin ESD
sensitive equipmentis required, suchas: Computers Printers Communication systems and cellular phones Video equipment
This deviceis particularly adpatedto the protection symmetrical signals.
MAIN APPLICATIONS

Application Specific Discretes
A.S.D.
FUNCTIONAL DIAGRAM
4 UNIDIRECTIONALTRANSIL™ FUNCTIONS. BREAKDOWN VOLTAGE VBR= 6.1V MIN LOW LEAKAGE CURRENT< 500 nA VERY SMALL PCB AREA< 2.6 mm2
FEATURES

The ESDA6V1P6isa monolithic array designedto
protectupto4 lines against ESD transients.
This deviceis ideal for applications where board
space savingis required.
DESCRIPTION
High ESD protection level. High integration. Suitablefor high density boards.
BENEFITS
IEC61000-4-2 level4:15kV (air discharge)kV (contact discharge) MIL STD 883E-Method 3015-7: class3
25kV HBM (Human Body Model)
COMPLIES WITHTHE FOLLOWINGSTANDARDS:
ESDA6V1P6
ELECTRICAL CHARACTERISTICS
(Tamb= 25°C)
Note1:
fora surge greater thanthe maximum values,the diodewillfailin short-circuit.
ABSOLUTE RATINGS
(Tamb= 25°C)
THERMAL RESISTANCES
ESDA6V1P6
1.1 25 50 75 100 125 150[T initial] / P[T initial=25°C)PPj PPj
Fig.1:
Relative variationof peak pulse power
versus initial junction temperature.
1000 10 100 (W)PP
Fig.2:
Peak pulse power versus exponential pulse
duration.
100.0 10 20304050 6070(A)PP
Fig. 3:
Clamping voltage versus peak pulse
current (typical values, rectangular waveform).
1.E-03
1.E-02
1.E-01
1.E+00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (A)FM
Fig.4:
Forward voltage drop versus peak forward
current (typical values). 234 56
C(pF)
Fig. 5:
Junction capacitance versus reverse
voltage applied (typical values).
2.0 50 75 100 125 [T] / I [T=25°C]Rj Rj
Fig.6:
Relative variationof leakage current versus
junction temperature (typical values).
ESDA6V1P6
TECHNICAL INFORMATION
Fig. A1:
Application example.
With the focusof lowering the operation levels, the
problemof malfunction causedby the environment critical. Electrostatic discharge (ESD)isa major
causeof failurein electronic systems.a transient voltage suppressor, ESDA6V1P6is ideal choicefor ESD protectionby suppressing
ESD events.It is capable of clamping the
incoming transienttoa low enough level such that
any damageis preventedon the device protected ESDA6V1P6.
ESDA6V1P6 serves asa parallel protection
elements, connected between the signal line and
ground.As the transient rises above the operating
voltageof the device, the ESDA6V1P6 becomesa
low impedance path diverting the transient current ground. ESD protection by ESDA6V1P6
The clamping voltageis givenby the following formula:
VCL =VBR +Rd.IPP shownin figure A2, the ESD strikes are clampedby the transient voltage suppressor.
Fig. A2:
ESD clamping behavior. havea good approximationof the remaining voltagesat both Vi/o side, we provide the typical dynamical
resistance value Rd.By taking into account the following hypothesis: >Rd and Rload >Rd have:Vi o V R V d =+ ×
The resultsof the calculation done VG= 8kV, RG= 330Ω (IEC61000-4-2 standard), VBR= 6.4V (typ.) and= 1.5Ω (typ.) give:Vi o Volts/.=428
This confirms the very low remaining voltage across the devicetobe protected.Itis also importantto note
thatin this approximation the parasitic inductance effect was not taken into account. This couldbea few
tenthsof volts duringa fewnsat the Vi/o side.
ESDA6V1P6
Fig. A3:
ESD test board.
Fig. A4:
ESD test configuration.
Fig. A5:
Remaining voltage during ESD surge. Crosstalk behavior
Fig. A6:
Crosstalk phenomenon
ESDA6V1P6
The crosstalk phenomena are dueto the coupling between2 lines. Coupling factors( β12or β21) increase
when the gap acrosslines decreases, particularlyin silicon dice.In the example above, the expected signal load RL2is α2VG2,in fact the real voltageat this point has gotan extra value β21VG2. This partof the VG1
signal represents the effectof the crosstalk phenomenonof the line1on the line2. This phenomenon hasbe taken into account when the drivers impose fast digital dataor high frequency analog signals. The
perturbed line willbe more affectedifit works with low voltage signalor high load impedance (few kΩ)
Fig. A7:
Analog crosstalk test configuration.
Fig. A8:
Typical analog crosstalk response.
Fig. A9:
Digital crosstalk test configuration.
Fig. A10:
Typical digital crosstalk response.
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