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EMIF03-SIM02F2 |EMIF03SIM02F2STN/a4430avai3 LINES EMI FILTER INCLUDING ESD PROTECTION


EMIF03-SIM02F2 ,3 LINES EMI FILTER INCLUDING ESD PROTECTIONPin Configuration (Ball side)1.42mm x 1.42mm■ Very thin package: 0.65 mm ■ High efficiency in ESD s ..
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EMIF03-SIM02F2
3 LINES EMI FILTER INCLUDING ESD PROTECTION
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MAIN PRODUCT APPLICATIONS:

EMI filtering and ESD protection for: SIM Interface (Subscriber Identify Module) UIM Interface (Universal Identify Module)
DESCRIPTION

The EMIF03-SIM02F2 is a highly integrated
devices designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic interfer-
ences. The EMIF03 flip chip packaging means the
package size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents the device from destruction when
subjected to ESD surges up 15kV.
BENEFITS
EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Lead free package Very low PCB space consuming:
1.42mm x 1.42mm Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reducing of parasitic elements through
integration & wafer level packaging.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4 on input pins 15kV (air discharge)
8kV (contact discharge)
Level 1 on output pins 2kV (air discharge)
2kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3
EMIF03-SIM02F2

3 LINES EMI FILTER
INCLUDING ESD PROTECTION
REV. 2October 2004
Figure 2: Configuration

IPAD™
Figure 1: Pin Configuration (Ball side)
TM: IPAD is a trademark of STMicroelectronics.
Table 1: Order Code
EMIF03-SIM02F2
Table 2: Absolute Ratings (limiting values)
Table 3: Electrical Characteristics (Tamb = 25°C)
EMIF03-SIM02F2
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Figure 3: S21 (dB) attenuation measurement
(A2-A3 line)
Figure 4: S21 (dB) attenuation measurement
(B1-B3 line)
Figure 5: S21 (dB) attenuation measurement
(C1-C3 line)
Figure 6: Analog crosstalk measurements
Figure 7: ESD response to IEC61000-4-2
(+15kV air discharge) on one input V(in) and on
one output (Vout)
Figure 8: ESD response to IEC61000-4-2 (-15kV
air discharge) on one input V(in) and on one
output (Vout)
EMIF03-SIM02F2
Figure 10: Aplac model
Figure 11: Aplac parameters
Figure 9: Line capacitance versus reverse
applied voltage (typical)
EMIF03-SIM02F2
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Figure 12: Ordering Information Scheme
Figure 13: FLIP-CHIP Package Mechanical Data
Figure 14: Foot print recommendations Figure 15: Marking
EMIF03-SIM02F2
Figure 16: FLIP-CHIP Tape and Reel Specification
Table 4: Ordering Information
Note: More informations are available in the application notes:

AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
Table 5: Revision History
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