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EMIF02-USB05F2 |EMIF02USB05F2STMN/a700avai2-line EMI filter and ESD protection with R pull-up, for USB interfaces
EMIF02-USB05F2 |EMIF02USB05F2STN/a13993avai2-line EMI filter and ESD protection with R pull-up, for USB interfaces


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EMIF02-USB05F2
2-line EMI filter and ESD protection with R pull-up, for USB interfaces
November 2006 Rev 2 1/7
EMIF02-USB05F2
AD™
2 line EMF filter including ESD protection
Main application

When EMI filtering is ESD sensitive equipment is
required: Mobile phones and communication systems Computers, printers and MCU boards
Description

The EMIF02-USB05F2 is a highly integrated array
designed to suppress EMI / RFI noise for USB
port filtering. The EMIF02-USB05F2 Flip-Chip
packaging means the package size is equal to the
die size.
Additionally, this low-pass filter includes an ESD
protection circuitry to prevent damage to the
application when subjected to ESD surges up 15 kV.
This device is designed to be fully compatible with
USB standards.
Benefits
2 x EMI low-pass filter + 2 line ESD protection 1.5 kΩ pull-up included High efficiency in EMI filtering Lead free package Very low PCB space consumption:
1.92 mm x 0.92 mm Very thin package: 0.65 mm High reliability offered by monolithic integration High reduction of parasitic elements through
integration and wafer level packaging USB full speed (12 Mbps), OTG compliant
Complies with following standards:
Pin configuration (bump side)
Functional diagram
Order code

TM: IPAD is a trademark of STMicroelectronics
IEC 61000-4-2
level 4 15 kV (air discharge)
8 kV (contact discharge)
MIL STD 883G - Method 3015-7 Class 3
Characteristics EMIF02-USB05F2
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1 Characteristics



Table 1. Absolute ratings (limiting values)
Table 2. Electrical characteristics (Tamb = 25° C)
EMIF02-USB05F2 Characteristics
3/7



Figure 1. S21 (dB) attenuation measurement Figure 2. Analog crosstalk measurements
Figure 3. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(Vin) and on one output (Vout)
Figure 4. ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
(Vin) and on one output (Vout)
Figure 5. Junction capacitance versus
reverse voltage applied
Ordering information scheme EMIF02-USB05F2
4/7
Figure 6. Aplac model device structure
Figure 7. Aplac model parameters Ordering information scheme
EMIF02-USB05F2 Package information
5/7
3 Package information
Figure 8. Flip-Chip package dimensions


Figure 11. Flip-Chip tape and reel specification
Figure 9. Foot print recomendations Figure 10. Marking
Ordering information EMIF02-USB05F2
6/7
Note: More packing information is available in the application notes
AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: “EMI Filters: Recommendations and measurements”
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOP ACK specifications are available at: .
4 Ordering information


5 Revision history


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